Toshiba Launches Industry’s Largest Embedded NAND Flash Memory Modules

32nm Embedded Memory up to 128GB NAND and Controller in a Single Package

By Nick Flaherty www.flaherty.co.uk
Toshiba has launched a 128-gigabyte (GB) embedded NAND flash memory module, the highest capacity yet achieved in the industry. The module is fully compliant with the latest e•MMC standard, and is designed for application in a wide range of digital consumer products, including smartphones, tablet PCs and digital video cameras. Samples will be available from September, and mass production will start in the fourth quarter (October to December) of 2010.

The new 128GB embedded device integrates sixteen 64Gbit (equal to 8GB) NAND chips fabricated with Toshiba's cutting-edge 32nm process technology and a dedicated controller into a small package only 17 x 22 x 1.4mm. Toshiba is the first company to succeed in combining sixteen 64Gbit NAND chips, and applied advanced chip thinning and layering technologies to realize individual chips that are only 30 micrometers thick.

Toshiba's modules now range from 2GB to 128GB and integrate a controller to manage basic control functions for NAND applications, and are compatible with the JEDEC e•MMC Version 4.4 and its features. New samples of 64GB chips will also be available from August.

Demand continues to grow for large density chips that support high resolution video and deliver enhanced storage, particularly in the area of embedded memories with a controller function that minimizes development requirements and eases integration into system designs.

New Product Line-up

Product Number	Capacity	Package	Sample Shipment	Mass Production
THGBM2T0DBFBAIF	128GB	237Ball FBGA 17x22x1.4mm	Sep. 2010	4Q, 2010 (Oct.-Dec.)
THGBM2G9D8FBAIF	64GB	237Ball FBGA 17x22x1.4mm	Aug. 2010	4Q, 2010 (Oct.-Dec.)

Key Features

1. The JEDEC e•MMC V4.4 compliant interface handles essential functions, including writing block management, error correction and driver software. It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products.

2. Embedded in a system, the module can record up to 2,222 hours of music at a 128Kbps bit rate, 16.6 hours of full spec high definition video and 38.4 hours of standard definition video

3. The 128GB device stacks sixteen 64Gbit chips fabricated with leading-edge 32nm process technology. Application of advanced chip thinning, layering and wire bonding technologies has allowed Toshiba to achieve individual chips only 30 micrometers thick, and to layer and bond them in a small package. The result is an embedded NAND flash memory module with the industry’s highest density.

4. The new products are sealed in a small FBGA package only 17 x 22 x 1.4mm and has a signal layout compliant with the JEDEC e•MMC V4.4.

Specifications

e•MMC

Interface	JEDEC e•MMCTM V4.4 standard HS-MMC interface
Power Supply Voltage	2.7V to 3.6V (memory core); 1.65V to 1.95V / 2.7V to 3.6V (interface)
Bus width	x1, x4, x8
Write Speed*	21MB per sec. (Sequential/Interleave Mode) 21MB per sec. (Sequential/No Interleave Mode)
Read Speed*	46MB per sec. (Sequential Mode/Interleave Mode) 55MB per sec. (Sequential/No Interleave Mode)
Temperature range	-25degrees to +85degees Celsius
Package	153Ball FBGA （+84 support balls）

Related articles

• Toshiba hits 128GB with new NAND flash memory (crunchgear.com)
• Samsung Introduces High-speed 512GB SSD Utilizing New Toggle-mode DDR NAND Memory (eon.businesswire.com)
• Toshiba To Test Sub-25-nm NAND Flash (hardware.slashdot.org)
• Samsung and Toshiba squeeze NAND market (go.theregister.com)

Arizona State stacks nanoscale memory chips

Researchers improve chip memory by stacking cells

Researchers at Arizona State University have developed an elegant method for significantly improving the memory capacity of electronic chips.
The researchers have shown that they can build stackable memory based on 'ionic memory technology' which could make them ideal candidates for storage cells in high-density memory. Best of all, the new method uses well-known electronics materials.
“This opens the door to inexpensive, high-density data storage by ‘stacking’ memory layers on top one another inside a single chip,” said Michael Kozicki, an ASU electrical engineering professor and director of the Center for Applied Nanoionics. “This could lead to hard drive data storage capacity on a chip, which enables portable systems that are smaller, more rugged and able to go longer between battery charges.”
“This is a significant improvement on the technology we developed two years ago where we made a new type of memory that could replace Flash, using materials common to the semiconductor industry (copper-doped silicon dioxide). What we have done now is add some critical functionality to the memory cell merely by involving another common materia – silicon.”
Kozicki outlined the new memory device in a technical presentation he made in November at the 2009 International Electron Devices and Materials Symposia in Taiwan. Kozicki said that given current technology, electronics researchers are fast reaching the physical limits of device memory. This fact has spurred research into new types of memory that can store more information into less and less physical space. One way of doing this is to stack memory cells.
Kozicki said stacking memory cells has not been achieved before because the cells could not be isolated. Each memory cell has a storage element and an access device; the latter allowing you to read, write or erase each storage cell individually.
“Before, if you joined several memory cells together you wouldn’t be able to access one without accessing all of the others because they were all wired together,” Kozicki said. “What we did was put in an access, or isolation device, that electrically splits all of them into individual cells.”
Up until now, people built these access elements into the silicon substrate.
“But if you do that for one layer of memory and then you build another layer, where will you put the access device,” Kozicki asked. “You already used up the silicon on the first layer and it’s a single crystal, it is very difficult to have multiple layers of single crystal material.”
The new approach does use silicon, but not single crystal silicon, which can be deposited in layers as part of the three-dimensional memory fabrication process. Kozicki said his team was wrestling with how to find a way to build a diode into the memory cell. The diode would isolate the cells.
Kozicki said this idea usually involves several additional layers and processing steps when making the circuit, but his team found an elegant way of achieving diode capability by substituting one known material for another, in this case replacing a layer of metal with doped silicon.
“We can actually use a number of different types of silicon that can be layered,” he said. “We get away from using the substrate altogether for controlling the memory cells and put these access devices in the layers of memory above the silicon substrate.”
“Rather than having one transistor in the substrate controlling each memory cell, we have a memory cell with a built-in diode (access device) and since it is built into the cell, it will allow us to put in as many layers as we can squeeze in there,” Kozicki said. “We’ve shown that by replacing the bottom electrode with silicon it is feasible to go any number of layers above it.
With each layer applied, memory capacity significantly expands.
“Stackable memory is thought to be the only way of reaching the densities necessary for the type of solid state memory that can compete with hard drives on cost as well as information storage capacity,” Kozicki said. “If you had eight layers of memory in a single chip, this would give you almost eight times the density without increasing the area.”

Related articles by Zemanta

• Intel's next-gen memory closer to reality (news.cnet.com)