Monday, June 27, 2016

Microchip adds independent peripherals to PIC32

By Nick Flaherty www.flaherty.co.uk

Microchip has launched its first family of PIC32 microcontrollers with periperhals that can run independently of the core. This is a big step, as it helps to reduce power and simplify the development and operation of nodes in the Internet of Things (IoT) .

The MIPS MicroAptiv-based PIC32MM family bridges the gap between the company’s popular PIC24F XLP and PIC32MX families. But what makes this more significant is that the new family is the first PIC32 to feature core independent peripherals, designed to offload the CPU for lower power and lower system design cost. The PIC32MM devices are supported by the Microchip MPLA Code Configurator (MCC) to help simplify and accelerate designs.

Today’s embedded applications targeting the Internet of Things (IoT), consumer, industrial control, and motor control require flexible MCUs that consume less power, are more cost effective and have smaller form factors. For applications demanding low power and longer battery life, the PIC32MM has sleep modes down to 500 nA. Applications with space constraints will benefit from the small 4x4 mm package options. The PIC32MM devices include core independent peripherals such as Configurable Logic Cells (CLC) and Multiple-output Capture Compare PWMs (MCCPs) which help enable sensorless BLDC motor-control applications.

To help accelerate evaluation and development, a new $25 PIC32MM processor plug-in module is available (MA320020), which plugs into the $130 Explorer 16 Development Board (DM240001). The entire family of PIC32MM devices is supported by the Microchip MPLAB ecosystem including MPLAB X IDE and XC32 compiler. The MPLAB Code Configurator, a plug-in to the MPLAB X, helps with easy peripheral set-up, device configuration and pin mapping.

The PIC32MM family is available in mass production today in 20-pin QFN and SSOP; 28-pin µQFN, QFN, SOIC, SSOP, SPDIP; 36-pin QFN; and 40-pin uQFN packaging. Devices are available in 16 KB, 32 KB, and 64 KB Flash variants.

For more information, visit Microchip’s Web site at www.microchip.com/PIC32MM

u-blox targets long life IoT wireless with world's first narrowband cellular module

By Nick Flaherty www.flaherty.co.uk

Swiss wireless  chip and module maker u-blox has launched the world’s first cellular radio module compliant to the 3GPP Release 13, Narrowband IoT (LTE Cat. NB1) standard, opening up the use of cellular networks for the Interent of Things for the first time. 

The module is designed for use in applications such as smart buildings and cities, utilities metering, white goods, asset tracking, and agricultural and environmental monitoring and operate for between 10 and 20 years from a single-cell primary battery which has just not been possible up until now. This will also drive up volumes and drive down costs to make cellular IoT cost effective. 

“u-blox has been an early pioneer of NB-IoT and we’ve worked closely with companies including Vodafone, Deutsche Telekom and Huawei to complete the first successful commercial trials of pre-standard NB-IoT in smart metering and parking applications," said Stefano Moioli, Director Product Management Cellular at u-blox. "These trials proved conclusively that NB-IoT networks operate far more efficiently than GPRS and we’re confident of the technology’s future because of the many advantages it offers over alternative approaches. We’re therefore pleased to be able to announce the world’s first fully 3GPP compliant module that will enable customers to take full advantage of this exciting technology.”
The SARA-N2 narrowband IoT module has a battery life of 10 to 20 years 
The SARA-N2 Narrowband IoT (NB-IoT) module (above) measures 16 mm x 26 mm in a land grid array (LGA) package using u-blox nested architecture, and allows simple upgrades from u-blox GSM, HSPA or CDMA modules and ensures future-proof, seamless mechanical scalability across technologies.

The SARA-N2 module provides secure, private communications over licensed spectrum with guaranteed quality of service. It supports peak downlink rates of up to 227 kbps and uplink rates of up to 21 kbps, which keeps the power down aand allows the ten to twenty year battery life. Simultaneous support for three RF bands means that the same module may be used in most geographic regions.
The NB-IoT provides lower device complexity, ultra-low power operation and support for up to 150,000 devices per single cellular cell. Most significantly, the technology offers a 20 dB link budget improvement over GPRS to give excellent performance under poor coverage conditions such as underground or inside buildings.

Compared with unlicensed spectrum Low Power Wide Area (LPWA) solutions, NB-IoT offers greater security and freedom from interference because it uses a licensed spectrum based network. Other advantages include lower latency than mesh networks, thanks to its point-to-point topology, the ability to run it adjacent to existing 2G and LTE networks - it needs just 200 kHz of bandwidth - and a higher transmit power limit, which improves reliability and range. It also allows for robust 2 way communication which means that features such as firmware upgrade over the air are achievable. NB-IoT also allows global roaming, which is not the case with localized unlicensed spectrum based technologies.

Samples of the SARA-N2 NB-IoT module are currently scheduled for Q4 2016, with full production planned for early 2017.

Friday, June 24, 2016

Chinese chip maker looks to the global powerline market for IoT

By Nick Flaherty www.flaherty.co.uk

An interesting story at EETimes Europe is demonstrating the global forces at work to provide the technologies for the Internet of Things. 

US power line communications (PLC) chip designer Semitech Semiconductor has teamed up with a Brite Semiconductor in Shanghai on a new generation of PLC chips that can handle both PLC and wireless communications around the world.
Brite has developed a communication core architecture SoC based around the Tensilica core from Cadence Design Systems and integrates DSP, memory, PLC AFE, RF transceiver and high-speed interface IPs with DDR and USB. This provides a dual-mode PLC/wireless communication system for machine to machine links over the power grid

The chip will be manufactured using an advanced process with SMIC, which helped set up Brite, and will contain Semitech's integrated PLC/wireless IP. This provides the dual-mode communication core (DMCC) including architecture, digital modules and algorithms that can simultaneously support reliable wireless and PLC connectivity for the M2M and Internet of Things (IoT) market. This IP is already used in machine-to-machine communication and IoT applications such as smart meters, street lighting, solar panels and remotely monitored and controlled industrial equipment, providing a core technology to implement a worldwide communications network over the existing power grid.

"This collaboration represents an important milestone for Brite, as designing an industrial SoC product for the emerging M2M market has been a goal of ours," said Jerry Ardizzone, senior vice president of worldwide sales and marketing for Brite Semiconductor. "The primary application for the Brite and Semitech collaboration will be smart meters, and we will develop additional solutions for broader industrial applications including smart home, smart grid and automotive."

"The next evolutionary step for smart grid applications is to move toward heterogeneous PLC/wireless networks, while accommodating aggressive cost and power budgets," noted Zeev Collin, CEO of Semitech Semiconductor. "Our existing PLC architecture and the extensive experience of our team in narrowband communication across different media make it possible to take this step. Partnering with Brite puts us at the leading edge of the M2M market and will ensure that we yield a superior product."

Brite Semiconductor was co-founded by Semiconductor Manufacturing International Corporation (SMIC) and Open-Silicon, as well as venture capitalist firms from China and Silicon Valley. As a strategic partners, SMIC provides Brite Semiconductor with 28nm process technology with high-end SoC design services,

www.semitechsemi.com,

Wednesday, June 22, 2016

The latest embedded power news and industry interview

By Nick Flaherty www.flaherty.co.uk

The latest power newsletter is out from EETimes Europe, with $4m for a new silicon graphene battery development, 3D packaging developed for data centre power, TI cutting the size and resistance of MOSFETs by up to 80% and the exclusive Power Trends Interview with Siobhan Dolan Clancy, the general manager of the discrete products division of Microsemi.
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Power news from EETimes Europe
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June 20, 2016
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LATEST NEWS

SiNode wins $4m to jumpstart silicon graphene automotive batteries
.SiNode wins $4m to jumpstart silicon graphene automotive batteries
Pi Innovo in three-way deal to create two speed electric drivetrain
.Pi Innovo in three-way deal to create two speed electric drivetrain
ABB in top five suppliers of charging stations in China
.ABB in top five suppliers of charging stations in China

TECHNOLOGIES TO WATCH

Silicon cones on perovskite boost hydrogen production for fuel cells
.Silicon cones on perovskite boost hydrogen production for fuel cells
Solar cells with high bifaciality developed
.Solar cells with high bifaciality developed
Collaboration targets 3D packaging for voltage regulators in data centers
.Collaboration targets 3D packaging for voltage regulators in data centers

NEW PRODUCTS

TI cuts 60 V MOSFET size by 80% with FemtoFET
.TI cuts 60 V MOSFET size by 80% with FemtoFET
Convection cooled 600 W supply boosts reliability by 25%
.Convection cooled 600 W supply boosts reliability by 25%
650V MOSFETs provide more headroom for industrial, telecom and renewable energy
.650V MOSFETs provide more headroom for industrial, telecom and renewable energy

POWER TRENDS INTERVIEW

Power Trends: Microsemi sees integration from device to module drive innovation

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NEW PRODUCTS

Li-ion battery pack monitor safeguards traction battery systems

Railway-certified 20W DC-DC converter has 4:1 input

Regulator module reduces board area in noisy applications

Ultra Compact AC-DC modules provide up to 5W for low power standby applicaitions

TECHNICAL PAPERS

Texas Instruments: Power conversion topology for space- constrained applications

Digital Power System Management - Take Control of Your Power Supplies

Intersil: Understanding USB-C Buck-Boost Battery Charging

EVENTS

Startups at Automatica 2016 Industrial Automation show – Munich, June 21 - 24

Visit our leading websites

Tuesday, June 21, 2016

Next generation RapidIO targets 10Gbit/s for scalable infrastructure

By Nick Flaherty www.flaherty.co.uk

RapidIO.org has launched the next generation of its interconnect architecture, targeting 25xN 100Gbit/s performance for 5G wireless and data centre infrastructure as well as industrial embedded systems.

With more than 200 million RapidIO fabric ports deployed worldwide at speeds of 6xN and 10xN 10-50 Gbit.s in analytics, wireless infrastructure, industrial and military applications, the 25xN 100 Gbit/s specification provides an open standard interconnect fabric for systems requiring heterogeneous coherent computing infrastructure that can scale with non-volatile storage.

“With the public release of the specification, our focus within our RapidIO.org Technical Working Group now shifts toward our Coherent Scale Out Task Group and our Non-Volatile Storage Task Group,” said Rick O’Connor, Executive Director of RapidIO.org. “Work on the Coherent Scale Out and Non-Volatile Storage draft specifications is progressing and we invite members of industry to join us and participate in defining these key building blocks for flexible, heterogeneous, coherent scale out of performance critical, low-latency applications over RapidIO fabrics.”

“The public release of the 25xN 100 Gbps RapidIO Specification is the culmination of efforts and contributions of RapidIO.org member companies,” said Paul Carson, Chairman of RapidIO.org and Director of IP Development at Texas Instruments. “This work extends the performance roadmap of RapidIO fabrics for use in heterogeneous systems for many years to come.”

The emergence of heterogeneous systems and next-generation non-volatile storage technologies beyond NAND Flash such as Resistive RAM (ReRAM) means fabric clusters will be key to driving scalable performance, says Dr. Zvonimir Z. Bandić,
Director of Next Generation Platform Technologies at drive maker Western Digital. “We see the public release of the 25xN 100 Gbps RapidIO Specification as a key enabling building block for these coherent, non-volatile storage based systems,” he said.

The technology will be integrated into embedded system-on-chip devices with cores from ARM and MIPS as a way to link different types of computing resources together with low latency using standalone switches from suppliers such as IDT.

Open standard interconnects are key to ongoing energy efficiency and performance improvements across the entire SoC,” said Phil Bourekas, director of segment marketing, ARM. “The public availability of the 25xN 100 Gbps RapidIO Specification addresses ARM ecosystem developer requirements for coherent network infrastructure SoCs based on the ARMv8-A architecture, providing an available standard for systems at 5G and beyond.”

“IDT has a strategic commitment to RapidIO that spans over a decade and the public release of the 25xN 100 Gbps RapidIO Specification is a key enabling platform for wireless, HPC, cloud and industrial systems our customers are building”, said Ron Jew, General Manager, Wireless Infrastructure Products at IDT. “Through key R&D collaborations with global technology experts, such as CERN openlab, we’re able to ensure that our heterogeneous coherent scale out and storage over 100 Gbps RapidIO fabrics delivers the performance our customers in 5G infrastructure and advanced data analytics are looking for.”


“Heterogeneous computing is becoming increasingly prevalent for our customers’ next generation systems and our MIPS processor technology plays a key role in these systems,” said Jim Nicholas, EVP MIPS Processor IP at Imagination Technologies. “The release of the industry open standard 25xN 100 Gbps RapidIO Specification is a welcome addition to our ecosystem and we’ll look forward to future developments from the Coherent Scale Out Task Group.”



Thursday, June 16, 2016

Bluetooth 5 bids for IoT in the home and office

By Nick Flaherty www.flaherty.co.uk

The next generation of Bluetooth promises to provide four time the range of the current versions with twice the bandwidth in a bid to create a “connectionlessIoT. The Bluetooth Special Interest Group (SIG) has reached a major milestone with 30,000 members using the technology in one way or another. Bluetooth 5 tackles some of the challenges that have held previous versions back in the roll out of IoT networks.

The new technology will be released later this year or early 2017 with significantly increased range, speed, and broadcast messaging capacity. Extending range will deliver robust, reliable Internet of Things (IoT) connections that make full-home and building and outdoor use cases a reality. Higher speeds will send data faster and optimize responsiveness. Increasing broadcast capacity will propel the next generation of “connectionless” services like beacons and location-relevant information and navigation. These Bluetooth advancements open up more possibilities and enable SIG companies – now at an all-time high of 30,000 member companies – to build an accessible, interoperable IoT.

“Bluetooth 5 will transform the way people experience the IoT by making it something that happens simply and seamlessly around them,” said Mark Powell, executive director of the Bluetooth SIG. “Increasing operation range will enable connections to IoT devices that extend far beyond the walls of a typical home, while increasing speed supports faster data transfers and software updates for devices. And now with the ability to broadcast a much richer set of information, Bluetooth 5 will make beacons, location awareness, and other connectionless services an even more relevant part of an effortless and seamless IoT experience”

DSP designer CEVA is already engaged with multiple customers whose silicon will incorporate these Bluetooth 5 features when the standard is finally ratified later this year.

“The advancements coming in Bluetooth 5 keep the technology at the forefront of innovation and will help to transform the way people interact with the Internet of Things, providing them a seamless experience that is both simpler and more relevant,” said Errett Kroeter, vice president of marketing for the Bluetooth SIG. “We are pleased to see the excitement and fast implementation of this new technology from SIG members like CEVA and others throughout the product value chain, which will ultimately bring Bluetooth 5 benefits to customers around the world in the shortest time.”

RivieraWaves is part of CEVA and is the leading IP vendor providing solutions for both Bluetooth low energy and Bluetooth dual mode (i.e. Bluetooth classic combined with Bluetooth low energy), with a long pedigree stretching back more than fifteen years. As a result, CEVA Bluetooth IP has shipped in more than a billion devices to date.

"We see very strong traction in the market for these features. Indeed, we already have some licensees with silicon prototypes implementing some of these Bluetooth 5 features and we look forward to the wide scale deployment of Bluetooth 5 in due course,” said Aviv Malinovitch, vice president and general manager of CEVA's Connectivity business unit.

The RivieraWaves Bluetooth IP platforms consist of a hardware baseband controller, plus a feature-rich software protocol stack. For Bluetooth low energy, this protocol stack encompasses the Link Layer up to the GAP/GATT plus a comprehensive set of Services and Profiles. For Bluetooth dual mode, this protocol stack presents an industry standard HCI interface. A flexible radio interface allows the platform to be deployed with either RivieraWaves RF or various partners’ RF IP, enabling optimal selection of foundry and process node.

Today, there are 8.2 billion Bluetooth products in use, but at least 4bn of these are the mobile phones that act as a terminal for a Bluetooth link. The SIG has ambitious plans that the enhancements in Bluetooth 5 and planned future Bluetooth technical advancements mean that Bluetooth will be in more than one-third of all installed IoT devices by 2020.

SIG membership has grown over 11 percent since the end of 2015, now reaching a record-high with its 30,000th member, Blossom Group, a startup that is building infrasound and low-frequency noise relaxation products.

“Implementing Bluetooth as our wireless technology and joining the SIG organization was the obvious choice to ensure our products’ success,” said Luke Sanger, CEO and co-founder of Blossom Group. “Bluetooth has the ubiquity of a trusted wireless communication platform and a great history of supporting market trends and working with developers and members to produce groundbreaking products and applications. We know Bluetooth will stay ahead of the game by working with its members and embracing technological advancements – from power efficiency to IoT connectivity – to push the limits of innovation.”

Software AG and Dell boost real time predictive maintenance across the Internet of Things

By Nick Flaherty www.flaherty.co.uk

Software AG and Dell has developed a new architecture for the internet of things (IoT) that allows enterprises to perform real-time streaming analytics at the edge of the network, close to digital devices and sensors. 

The system uses Dell’s Edge Gateway 5000 Series combined with an embedded version of Software AG’s Apama Streaming Analytics (below). Performing real-time analytics on the edge can drastically reduce the cost of high volume Industrial IoT sensor traffic and the need for expensive central servers. This architecture also allows for the rapid deployment of edge analytics, and reduce the cost of IoT projects. This first joint Dell and Software AG solution focuses on preventative and predictive maintenance, with further IoT use case solutions to follow in the near future.



“This brings a new dimension and meaning to leading-edge technology,” said Frank Schiewer, Software AG SVP Global Alliances & Channel. “With Dell, we are bringing the competitive advantages driven by the internet of things to a much wider audience through reduced costs and increased adoption speed. Co-innovation is the name of the IoT game and this is a great example of two innovative companies partnering to provide ground breaking solutions. I look forward to widening the scope of this partnership over the coming months.”

Together, Dell and Software AG have created a Predictive Maintenance Blueprint entitled “Six steps to using the IoT to deliver maintenance efficiency” to help companies address their top operational challenges. This ensures that perishable data is acted on immediately by generating alerts, implementing an automated response on the Edge and ensuring that only meaningful data is sent to the cloud to minimize consumption of network bandwidth. This reduced data set can be integrated with historical data at the core and longer term trends and events identified and predicted.

“With our partners such as Software AG, we are lowering the barriers to IoT market entry for enterprises of all sizes and cutting the time needed to deploy IoT analytics significantly,” said Jason Shepherd, director, strategy and partnerships, Dell. “The IoT can now deliver its promise quickly, cost effectively and make a real contribution to driving economic growth.”

With estimates ranging from 15 to 40 billion new sensors being installed by 2020, it is imperative that real-time streaming analytics, driving automated decisions and responses, be located as near to the Edge as possible. The architectural benefits of distributed real-time analytics are decreased latency times for real-time events, a significant reduction in network traffic and a reduction in the central server power needed to cope with tens or hundreds of thousands of sensors. This fully scalable and flexible new architecture makes decisions on the Edge when appropriate and at the core when needed.

“Software AG always focuses on keeping customer choice open and the solutions built on this new architecture offer customers maximum flexibility in building IoT applications,” added Schiewer. “A common set of streaming analytic tools at the edge and in the core and automated decisions made where needed combines effectiveness with efficiency.”

New process boosts ESD protection

By Nick Flaherty www.flaherty.co.uk

Electrostatic discharge (ESD) can be a major problem for embedded equipment. Static generated from everyday movement can damage silicon devices, especially as process technology means feaatures in the chips are ever smaller and more vulnerable to such electric shocks

Toshiba is hoping a new process technology it has developed to increase resistance to Electrostatic Discharge (ESD) in devices will help.

The 0.13μm process technology at New process boosts ESD protection | EETE Power Management optimizes the structure of transistor and significantly improves ESD characteristics by a factor of four, while the standard deviation is only 1/12 that of the conventional structure. Analysis of 3D simulations has also allowed Toshiba to identify a mechanism for optimizing transistor structure to boost ESD robustness.

ESD protection devices are required to protect internal circuit and this is particularly true for analogue power semiconductor devices required to apply 10V to 100V, which need a high rated voltage. In this case, ESD protection devices must ensure high current flow, which results in enlarged chip size. Shrinking the size of the ESD protection device is an issue in realizing more compact chips.

Using 3D simulation analysis of an ESD event, Toshiba found out that ESD induced destruction is caused by lattice temperature increase due to the current flowing at the highest electric field point. Modifying the transistor structure, which extending the drain low resistive region to the source direction and suppressing the lateral silicon resistance, shifts the current flow from the bottom of the drain to source direction and detaches it from the highest electrical field point. This optimized design was found to increase ESD robustness by up to four times and to decrease the standard deviation down to 1/12. In addition, the device size required to ensure a HBM (Human Body Model) of ±2000V was cut by 68%.

Toshiba offers advanced analog process platforms, with 0.13μm process technology, that can be embedded with the transistors such as CMOS, DMOS, bipolar transistor and the passive devices such as resistor and capacitor. User can select a process suited to each application from three process platforms: “BiCD-0.13” is mainly for automotive (DMOS line up is up to 100V); “CD-0.13BL” is mainly for motor control drivers

Wednesday, June 15, 2016

ST chip boosts IoT security in any design

By Nick Flaherty www.flaherty.co.uk

To help tackle the challenge of securing the Internet of Things (IoT), ST has launched a separate security chip that can connect to any microcontroller via an I2C link.

The STSAFE-A100 can be designed-in by developers to provide security to Common Criteria EAL5+ without specialist security expertise through a comprehensive support ecosystem.

The STSAFE-A100 provides strong authentication services (see figures below) that help make sure only authorized IoT devices can access online services and only authorized accessories or consumables are recognized and accepted by an application. Interestingly, it is also compliant with the USB Type-C device-authentication scheme and secures communications with a remote host using Transport Layer Security (TLS) handshaking.

The chip uses a custom secure microcontroller (ST hasn't said which type of controller - the company uses the ARM SecureCore in other devices such as the ST19 and ST33 families) with its own embedded operating system that is certified to EAL5+, base don the company's experience in chips for highly secure banking and mobile phone billing systems.



Additional functions in the chip that further minimize any potential for security breaches include signature verification to ease secure boot and firmware upgrade, secure counters that allow usage monitoring, secure pairing with the host application processor, wrapping and unwrapping of local or remote host envelopes, and on-chip key-pair generation.

The STSAFE-A100 supports asymmetric cryptography including Elliptic Curve Cryptography (ECC) with NIST or Brainpool 256-bit and 384-bit curves, and symmetric cryptography using AES-128/AES-256. The STSAFE-A100 comes with a unique serial number on each die and its operating system comprises a kernel for authentication and data management and provides strong protection against logical, fault, side-channel and physical attacks.

“STSAFE-A100 delivers an economical and certified solution for state-of-the-art security in IoT and brand protection, presenting an alternative with clear advantages over existing approaches like software-based security running on a general-purpose microcontroller or an uncertified crypto-companion IC,” said Laurent Degauque, Marketing Director, Secure Microcontroller Division, MDG Group, STMicroelectronics. “Seamless integration puts security at the heart of the product and frees developers to focus on maximizing added value at the application level.”

ST has made design-in of its new secure element easy for customers by providing a complete ecosystem that includes an expansion board with Arduino headers, a microcontroller library, and reference implementations. These simplify attaching the STSAFE-A100 to a microcontroller such as any from the STM32 family.

The STSAFE-A100 secure element is scheduled to enter volume production in July 2016, as a 4mm x 5mm SO8N or 2mm x 3mm UFDFPN8.

Tuesday, June 14, 2016

Weightless and ETSI partner on low cost wireless standards for IoT

By Nick Flaherty www.flaherty.co.uk

One of the promising narrowband wireless protocols for the Internet of Things, Weightless, is moving towards an international standard.

The Weightless SIG is partnering with the European Telecommunications Standards Institute (ETSI), and a key ultra narrow-band (UNB) LPWAN technology and applications provider, Telensa, is to the board of the Weightless SIG.

In a move widely acknowledged to bring much needed consolidation to the LPWAN space the Weightless SIG will immediately offer its Weightless-N standards activities into the ETSI LTN initiative within TG28, ensuring that all those interested in UNB solutions are represented in a single forum.
This is the first step on standardisation and the move is supported by several other UNB technology companies (announcements to come). Weightless is supported by Neul which in September 2014 was acquired by Huawei.

ETSI is a globally accepted standards development organisation within which the Low Throughput Network (LTN) initiative is developing a standard for LPWAN. This initiative is supported by a number of significant companies including Telensa and Sigfox. ETSI LTN is concentrating on a UNB standard.

There are only two standards bodies that have developed IoT specific standards for unlicensed spectrum based on UNB technology – ETSI and the Weightless SIG.

“In order to reduce fragmentation and enable critical mass in the marketplace we are bringing these two initiatives together, immediately reducing fragmentation and providing a platform around which industry can coalesce,” said Weightless CEO, Professor William Webb. 

Telensa's vertical smart city solutions include smart street lighting, where it now has a footprint of over 1 million lights across the world. Telensa's solutions are based on its own 2-way UNB technology, which it has been progressing to a standard with ETSI for the past 2 years.

"Proprietary ecosystems are no substitute for credible open standards when real market velocity is required, said Will Gibson, CEO of Telensa. "That's why we're delighted to be extending our ETSI standards work by joining the board of Weightless. This partnership signals a growing maturity in the LPWA market and will liberate a new wave of smart city sensor and application developers.”

Low Power Wide Area networks are set to become an integral building block for a variety of connected products and services. Deploying such networks also in unlicensed spectrum is critical to ensuring that the market for IoT connectivity will remain sufficiently competitive. The initiative is important, because it can open up a whole new level of scale benefits to players that are driving the unlicensed networks forward.

Weightless will focus on certification, the eco-system development, marketing and information dissemination and other relevant activities to aid the widespread success of the ETSI standards. It is part of a series of moves by the Weightless SIG to bring consolidation and order to the IoT connectivity technology space.


weightless.org
telensa.com

Open source hypervisor port to MIPS processors brings more security to the IoT

By Nick Flaherty www.flaherty.co.uk

German software developer Kernkonzept has ported the open source L4Re hypervisor to the OmniShield ready MIPS CPUs from Imagination Technologies in a bid to mke IoT applicatiins more secure.

The small footprint L4Re hypervisor, maintained by Kernkonzept, can take advantage of the hardware virtualization technology in MIPS CPUs for more efficient context switching and better use of CPU cycles, leading to improved application headroom and security.

Hardware virtualization is quickly gaining attention beyond its traditional home in the data-center for the benefits it provides across numerous application areas from IoT to consumer to automotive to industrial and beyond. With this technology, connected devices can be designed with numerous distinct domains in which multiple operating systems and applications can run independently at the same time on a single platform.

The L4Re operating system is an open-source system framework for building applications with real-time, security, safety, and virtualization requirements, and the latest update includes a new portable virtual machine monitor called ‘uvmm’ with support for both MIPS and ARM virtualization technology

The OS is built on the principle of a minimal Trusted Computing Base: minimising an application’s attack area by modularization and by reducing its dependencies. It consists of the L4Re hypervisor/microkernel, user-level infrastructure for building trusted native L4Re microapps, and virtual-machine support for running various standard OSes in isolated compartments.

The MIPS OmniShield technology uses the hardware virtualization in the CPU to create multiple domains on a single SoC and this allows the L4Re operating system to consolidate multiple applications with differing security, safety, or real-time requirements. This means multiple isolated tenants or guests can run on the same host, authorizing access to on-chip resources, prioritizing use of shared resources, allocating and managing service interrupts from external sources and peripherals.

“As Imagination continues to expand its MIPS ecosystem and OmniShield security offerings, we are delighted to work with Kernkonzept to bring the proven, highly efficient L4Re hypervisor to MIPS. Open source technologies like L4Re, where entire communities are responsible for developing and maintaining the code, can lead to inherently more reliable systems. We’re seeing a great deal of interest in L4Re for MIPS,” said Jim Nicholas, EVP MIPS Processor IP at Imagination.

Kernkonzept develops the open-source L4Re operating systems and hypervisor for security/safety-critical and virtualization-enabled applications. The Dresden, Germany-based company provides software services for the security-sensitive, real-time, and embedded markets.

“The collaboration is enabling us to take the L4Re operating system into new areas. This technology is already quite strong in areas including government and military. Now it’s making its way into embedded markets such as Wi-Fi routers, cable set-top boxes, home gateways, and automotive where MIPS CPUs have a strong presence,” said  Michael Hohmuth, CEO of Kernkonzept.

The open source prpl Foundation has created a demonstration vehicle that enables companies to see and try out the capabilities of hardware virtualization for themselves. It illustrates the power of a separation-based architecture in providing reliability and ease-of development for next-generation connected devices.

The demonstration builds on prpl’s proof-of-concept demonstration earlier this year of its prplSecurity framework—a comprehensive collection of open source APIs providing hardware-level security controls. That was one of the first public demonstrations of hardware enforced multi-tenant OpenWrt, the Linux distribution at the heart of most of the world’s home gateways.

The new demonstration features several domains including two instances of OpenWrt – one that isolates the Wi-Fi radio, and another that enables access to networking devices. With evolving Wi-Fi channel and frequency regulations, it’s important to ensure the radio is completely isolated, while letting users update their OS and install their own applications on the system. Additional domains can be used for provisioning of third party services such as those from operators and service providers.

The L4Re hypervisor for MIPS is available now at www.kernkonzept.com/download.html. Kernkonzept also provides a supported version of the L4Re hypervisor. 

Monday, June 13, 2016

Programmable Drag-and-drop analogue chip for multiple sensors in the IoT

By Nick Flaherty www.flaherty.co.uk

Cypress Semiconductor has launched a new programmable system-on-chip that simplifies the design of next-generation industrial, home appliance and consumer systems that require multiple sensors. 

Many Internet of Things (IoT) applications require multiple sensors and can benefit from dedicated coprocessors that offload sensor processing from the host and reduce overall system power consumption. At the same time the analogue element of the design is often a challenge. The new PSoC Analogue Coprocessor integrates programmable analogue blocks, including a new Universal Analogue Block (UAB), which can be configured with GUI-based software components. 

Based on a 32-bit ARM Cortex-M0+ signal processing engine, it delivers a fully programmable analog front end with op amps, programmable gain amplifiers, analog multiplexers, analog-to-digital converters, analogue filters and digital-to-analogue converters (DACs). This simplifies the design of custom analogue front ends for sensor interfaces by allowing engineers to update sensor features quickly with no hardware or host processor software changes, while also reducing overall costs.

For example, in home automation applications, engineers can easily configure the coprocessor to continuously monitor multiple sensors, such as temperature, humidity, ambient light, motion and sound, allowing the host to stay in a standby low-power mode. Future design changes to support new sensor types can also be easily implemented by reconfiguring the programmable analog blocks. 

The design of custom sensor interfaces is handled by Cypress’s free PSoC Creator Integrated Design Environment (IDE), which simplifies system design by enabling concurrent hardware and firmware development using PSoC Components—free embedded ICs represented by an icon in the IDE. Engineers can easily configure the programmable analog blocks in the Analogue Coprocessor by dragging and dropping components on the PSoC Creator schematic and customizing them with graphical component configuration tools. The components offer fully engineered embedded initialization, calibration and temperature correction algorithms.

“The PSoC Analogue Coprocessor makes sensor interface design accessible to embedded systems engineers without requiring expertise in analog system design; this comes with the added benefit of enabling rapid prototyping and design iterations in software with no hardware changes by simply modifying components in PSoC Creator,” said John Weil, vice president of MCU marketing at Cypress. “Cypress has pioneered and perfected programmable analog technology for 15 years, and now our PSoC Analog Coprocessor provides the most programmable analog IP per square millimeter in a tiny chip-scale package.”

The PSoC Analog Coprocessor is available in a 3.7-mm by 2.0-mm chip-scale package option and is currently sampling with production expected in the fourth quarter of 2016. Parts will be available in 45-pin CSP, 28-pin SSOP, 48-pin QFN and 48-pin TQFP packages.

IAR adds static analysis and firmware integration for Renesas RX chips

By Nick Flaherty www.flaherty.co.uk

IAR Systems has launched a new version of its Embedded Workbench for the Renesas RX family of controllers that includes extended static code analysis through the powerful add-on tool C-STAT and the ability to easily import Renesas Firmware Integration Technology (FIT) modules.

The highly requested tool C-STAT is fully integrated in version 2.90 of the complete C/C++ compiler and debugger toolchain and performs advanced static analysis on the source code level. The updated version adds approximately 150 new checks to the existing wide range of checks, including 90 new MISRA C:2012 checks and two new packages of checks. 

Several new options are also available, for example the possibility to enable or disable the false-positives elimination phase of the analysis as well as to exclude files from the analysis. It not only aids developers in ensuring the code quality early in the development cycle, it also detects defects, bugs, and security vulnerabilities as defined by CERT C/C++ and the Common Weakness Enumeration (CWE), as well as helps keeping code compliant to coding standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012.

Renesas FIT is a technology that simplifies development of RX-based applications and improves portability between RX microcontrollers. It consists of a Board Support Package (BSP), peripheral function modules, middleware modules, and interface modules. The latest version of IAR Embedded Workbench for Renesas RX adds a tool for easy import of FIT modules. With this new integration, developers can use the imported FIT modules in IAR Embedded Workbench without having to make any adaptions to the imported code.

IAR Embedded Workbench for Renesas RX offers the IAR C/C++ Compiler, assembler, linker, library tools and the C-SPY Debugger in one single IDE. It provides everything developers need to create smaller, faster, and smarter code for all Renesas RX MCUs. 

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