Thursday, September 17, 2015

UltraSoC adds deadlock detection to its SoC analysis, debug and profiling tools

By Nick Flaherty

One of the biggest challenges with developing software for embedded systems is deadlocks, where processors hang or stall as a result of complex interactions of the data. While this is traditionally tackled at the board level with a probe and logic analyser, it's a nightmare when the system is all inside a chip.

So when Cambridge-based tool developer UltraSoC adds deadlock detection capabilities into its embedded system-on-chip (SoC) analysis, profiling and debug, it's a big thing. The new analysis features allow embedded SoC architects, developers and debug engineers to detect and diagnose those hard-to-find corner cases which can cause complex SoCs to hang or stall intermittently and unpredictably, sometimes after days of continuous normal operation.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs,” said Gadge Panesar, chief technology officer of UltraSoC. “These conditions are a major contributor to the current crisis in the SoC industry. Conventional approaches either ignore the problem, or attempt to deal with it by generating massive, unmanageable data sets. UltraSoC takes a smarter approach, focusing on generating meaningful, actionable information; for the first time chip design teams can truly understand the behaviour of today’s complex SoCs.”

Bus deadlocks occur when a processor is waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives. Traditionally, the only way of isolating such problems has been to attempt to continuously trace and output all bus activity, requiring a high-bandwidth off-chip connection to gather the data, and difficult offline analysis software of huge data-sets. The UltraSoC technology uses a “smart” on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

This allows chip designers to efficiently and intelligently “look inside” their products, at wire speed, during normal operation, rather than having to pull out a trace of all the activity and go over millions of data points. The new deadlock detection capabilities are targeted at particularly difficult conditions that can cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

Software deadlocks are increasingly common in today’s SoCs. In a typical scenario, two different software processes might use a locking mechanism to govern shared access to common on-chip resources: for example another core, hardware peripherals or the capabilities of another software process. Problems can arise when each CPU believes that the other has locked its access to the shared resources. In this case UltraSoC provides an on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important. A key advantage is that UltraSoc is not tieed to any one architecture, supporting many different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others), making it possible to solve these situations.

SoC debug and silicon validation are key challenges facing the global electronics industry today. UltraSoC’s technology creates an on-chip debug infrastructure that enables pre- and post-silicon debug, reducing the risks in chip design, improving time-to-market, increasing quality and reducing costs.

Wednesday, August 19, 2015

IoT design competition winners show breadth of embedded design

Three winners of a competition to design systems for the Internet of Things show the innovation of embedded systems.

By Nick Flaherty

The three “Your IoT” design contest winners include Christian Klemetsson, Hoang Nhu and Ekawahyu Susilo.

•       Christian Klemetsson designed his “DeviceRadio” industrial automation solution to connect the real world to applications through virtual wires specifically within the industrial automation market. The goal of this product design is to deliver a custom IoT device on a solderless breadboard and controlled through the Internet in three minutes or less.
•       Hoang Nhu developed a platform for extending the IoT through all parts of the home, from medication reminders to smart power plugs. The Apple HomeKit SmartHome and Wellness IoT Development Platform monitors home environments/energy consumption and daily activities to optimize home appliance settings as well as make recommendations and reminders for optimal wellness.
•       Ekawahyu Susilo rounded out the winners with “Snappy,” (below) - a modular robotics platform designed to help teachers engage students through science, technology, engineering and math (STEM) education. Snappy can be used for a variety of science project applications such as determining altitude with water bottle rockets, measuring collision impact in physics experiments, and building a simple local/Internet-connected weather station with humidity and temperature sensors.

The competition was backed by distributor Digi-Key and chip designer Silicon Labs. Digi-Key supplied $10,000 worth of Silicon Labs components to each winner, who will select the Silicon Labs components they need (microcontrollers, wireless chips, sensors, boards and more) to bring their prize-winning IoT ideas to market as commercially viable products.

Contestants entered their IoT design at where all entries were initially voted on by site viewers. The top 15 entries were then judged using the following criteria: innovative application of technology, marketability of the product and the unique nature of the product, with bonus points awarded for a prototype.

“The IoT is the engine driving the growth and future of electronic component usage,” said David Sandys, director of technical marketing for Digi-Key. “Digi-Key could not be happier with the level of participation in the contest and being able to partner with Silicon Labs. The excitement really begins now, when we get to see where the winners will take their designs.”

“Developing connected ‘things’ for the IoT requires a combination of technical prowess, innovative design, and energy-friendly components and application development resources,” said Peter Vancorenland, vice president of IoT engineering at Silicon Labs. “We applaud the three contest winners for their outstanding IoT designs and wish them great success in bringing their inventive ideas to market using semiconductor and software solutions from Silicon Labs and Digi-Key.”

See the winners here

Thursday, January 08, 2015

10 Reasons Why Analytics Are Vital to the Internet of Things

10 Reasons Why Analytics Are Vital to the Internet of Things:

"This year has seen the software at the very highest point in the Internet of Things stack -- analytics -- becoming tightly coupled with the embedded devices at the edge of the network, leading to many different approaches and providers. Being able to monitor and use the data that comes from the Internet of Things is a huge potential challenge with different providers using different architectures and approaches, and different chip and equipment vendors teaming up in a range of different ways."

Slideshow on EETimes by Nick Flaherty

Tuesday, December 02, 2014

Cypress and Spansion in $4bn merger

By Nick Flaherty

Blimey! Cypress and Spansion are to merge in a $4bn deal that will change the landscape of the embedded market and potentially mark more consolidation. The key area for this deal is of course memory - Spansion was the spin off of AMD's flash memory business, while Cypress started out making SRAMs and has since moved into other controller-based devices. 
As a result the combined company will have annual turnover of $2bn and be the leader in SRAM and in NOR flash, and be a major player in microcontrollers - Cypress is well established in ARM-based microcontroller designs alongside its PSoC capacitative touch screen controller, while Spansion has recently been adding ARM cores to its memory devices. 
Although the deal is pitched as 50/50 - which is itself often a problem for deciding the direction going forward - it actually looks like a Cypress takeover.  Cypress founder and long term CEO TJ Rodgers will be CEO of the merged company while Ray Bingham of Spansion will be non-executive chairman and the company will be called - wait for it - Cypress Semiconductor. 
“This merger represents the combination of two smart, profitable, passionately entrepreneurial companies that are No. 1 in their respective memory markets and have successfully diversified into embedded processing,” said Rodgers, Cypress’s founding president and CEO. “Our combined company will be a leading provider of embedded MCUs and specialized memories. We will also have extraordinary opportunities for EPS accretion due to the synergy in virtually every area of our enterprises.”
The merger is expected to achieve more than $135 million in cost synergies on an annualized basis within three years and to be accretive to non-GAAP earnings within the first full year after the transaction closes. The combined company will continue to pay $0.11 per share in quarterly dividends to shareholders.
“Bringing together these high-performing organizations creates operating efficiencies and economies of scale, and will deliver maximum value for our shareholders, new opportunities for employees and an improved experience for our customers,” said John Kispert, CEO of Spansion. “With unparalleled expertise, global reach in markets like Japan and market-leading products for automotive, IoT, industrial and communications markets, the new company is well positioned to deliver best-of-breed solutions and execute on our long-term vision of adding value through embedded system-on-chip solutions.”
The closing of the transaction is subject to customary conditions, including approval by Cypress and Spansion stockholders and review by regulators in the U.S., Germany and China. The transaction has been unanimously approved by the boards of directors of both companies. Cypress and Spansion expect the deal to close in the first half of 2015. 

What other consolidation will happen remains to be seen but memory companies particularly will be vulnerable - the most notable recent deal was Global Foundries being paid to take on IBM's semiconductor business. I expect to see some other 'mergers' based around the Internet of Things as companies position themselves for growth i the next few years.

Wednesday, October 29, 2014

Fake Chip Furor Challenges Counterfeiters

Fake Chip Furor Challenges Counterfeiters | EE Times:

By Nick Flaherty

Glasgow-based USB chip designer FTDI is facing a storm of criticism after a new driver was released for its FT232R USB-to-UART bridge chip, but the problem was not with FTDI's chip.

Instead it was with counterfeit devices that people had bought over the Internet thinking they were genuine FTDI parts. The driver did not work with fake chips, effectively "bricking" people's USB interfaces, and highlighting the problem that many embedded chip maker face with counterfeit parts.  

FTDI has responded well. "We have temporarily suspended the driver from being downloaded. We will investigate what is happening in the current driver and, in the fullness of time, reinstate the driver download, and if there's something we need to alter in the driver, we will do that," said Gordon Lunn, global customer engineer support manager at FTDI. 

He points out that mainstream customers haven't had a problem and that this becomes an opportunity to remove fake devices from the supply chain and replace them with genuine parts. "We want to take the positives from this and work with people that want to buy genuine parts, and we are sorry if we have inconvenienced people who thought they were buying genuine parts, and we'd like to work with people to stop it at the source," he said. "We take each case on an individual basis. If a customer is willing to work with us and help us track down the source, then perhaps we would enter negotiations on a goodwill basis. I can't rule out working with individuals. It has to be considered."

"Ultimately, we are challenging the counterfeiters," Lunn said. "We want to maintain the quality and supply chain. Our distributors all have an investment in FTDI, which we are trying to protect, and we test our parts so that we produce the best output with genuine devices."
The company doesn't want its products to be compatible with "nongenuine devices," he said. "They've not had to invest in IP or driver development. There's no marketing collateral. There's no certification test, so they save a lot of expense." However, the company has specifically said there is no "fake detection" algorithm in the driver.
There is also a potential security issue (highlighted last month at EETimes) with microcontroller-based USB devices being reprogrammed with malware. "Our understanding is we think they are microcontroller based, so they are potentially more vulnerable," Lunn said. "You can't change what a genuine device actually does."
This is also important to FTDI's brand. "The reliability of these unknown devices is also unknown, so you can't guarantee how long they will last," he said. "But people still come back and think it's the FTDI parts failing, so we have to try to weed them out if we can."

Friday, May 23, 2014

Apps move into IoT design

English: Comparison of an Overo COM and a coin
English: Comparison of an Overo COM and a coin (Photo credit: Wikipedia)
Imagination Technologies is placing apps at the heart of its push to get the MIPS architecture adopted for the Internet of Things.

By Nick Flaherty

It is making its innovative FlowCloud technology available via an Android and iOS app to developers, including the maker community, hobbyists and students, to speed application development for the IoT. FlowCloud support will be available on several low-cost development boards with MIPS CPUs across
a range of operating systems, starting with a Microchip-based chipKIT WiFire board from Digilent.
The chipKIT WiFire board is a development platform that uses Microchip’s 32-bit PIC32MZ microcontroller with a MIPS microAptiv CPU. Imagination and partners will deploy FlowCloud support for other MIPS-based Android/Linux development boards in the near future.
The board is accessed and configured via the FlowCloud Getting Started app through an intuitive user interface that is intended to make embedded IoT development easier. A user’s FlowCloud account is free-of-charge and allows up to five connected devices.
FlowCloud provides an application-independent underlying platform that enables rapid construction and management of machine-to-machine and man-to-machine connected services through a set of modular infrastructure capabilities and underlying services that provide building blocks to accelerate deployment of cloud based applications. The infrastructure also provides secure asynchronous messaging and end-to-end connection establishment. The baseline FlowCloud service includes registration, authentication, association, security, notifications, updates and remote control. Optional plug-ins to accelerate time to market include FlowTalk (VoIP), FlowFunds (payments), and others. 
This allows users to build a wide range of applications, including security, personal and professional health monitoring, energy management, and cloud-based systems for content delivery as FlowCloud technology minimizes the resources required to make a product fully connected, bringing together people, devices and services in a platform for easily building connected applications and businesses.
“Imagination provides complete IP solutions and comprehensive platforms that speed development time for our customers, their customers and developers,” said Tony King-Smith, EVP marketing at Imagination. “FlowCloud is a unique and powerful offering for developers and the industry, and is proven and mature, having already deployed in volume. The new work we are doing with low-cost MIPS-based development boards extends the FlowCloud ecosystem and makes the platform far more accessible to developers.”
Most chipKIT platforms are hardware compatible with many existing Arduino shields, and existing code examples and reference materials are easily migrated. This gives the user a large base of options they can
utilize in the development process. The chipKIT WiFire is only available through Digilent and builds on the previous chipKIT development boards with a significant processor performance increase over the previous generation.
“Every day, more and more embedded systems are adding Internet connectivity, and the new chipKIT WiFire with our latest high-performance PIC32MZ MCU, which uses the microAptiv core, provides an ideal platform for IoT development,” said Rod Drake, director of Microchip’s MCU32 Division. “The
PIC32MZ and MPLAB Harmony software framework were designed for high-end, next-generation embedded applications that require high levels of performance, memory and advanced-peripheral integration. The addition of FlowCloud provides even more value for IoT and cloud applications.”

Users can get started with FlowCloud for the chipKIT WiFire at The chipKIT WiFire is priced at $79 (U.S.), and can be ordered today from Digilent at

From EETimes Europe
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Thursday, May 01, 2014

Startup Thalia DA uses ant algorithms to improve analogue and power designs

Bath startup Thalia Design Automation has raised its first equity funding to commercialize natural algorithms such as those used by ants for analogue, mixed signal and power design tools and is set to launch the beta versions of two new tools.
The key is that the Amalia and Emera tools use algorithms borrowed from natural processes such as ant movements to optimize placement and routing in these designs. This is traditionally regarded as a black art, needing highly skilled and scarce engineering resource, relatively long design cycles and often multiple design iterations to get to a production product, so using natural algorithms is a way to automate the design process further. Optimizations which typically took several days to weeks to complete can now be performed in a matter of hours says the company.
 “Analogue design methodology has remained unchanged for a long time,” said founder and CEO Sowmyan Rajagopalan. “I have seen the technical and time consuming efforts analogue designers have had to live with in order to design and optimise their circuits. Thalia’s tools will enable users to meet more challenging design requirements within shorter time frames. Custom chip design companies will benefit from reduced design times, shortened redesign cycles, better performing parts and more effective use of scarce skilled design resource.”
A further benefit is that the toolsets can be used to rapidly retarget existing designs to alternative silicon foundries for cost reduction and sourcing flexibility.
Thalia has now completed its initial equity funding round with Mercia Fund Management and Finance Wales. In addition the company has secured grant support from the Technology Strategy Board (TSB) and the Welsh Government.
“We are extremely pleased to have invested in a company that has developed solutions that not only address a technical challenge but also bring productivity gains for customers,” said Everard Mascarenhas, Investment Manager at Mercia Fund Management. “Thalia has developed a truly disruptive technology in a multi-billion dollar worldwide market where the incumbents grow and expand their offer through acquisition.”
Thalia provides two suites of EDA design tools; AMALIA, an intelligent analogue design optimisation & automation toolset and EMERA, a unique power device optimiser, schematic and layout generator. As well as offering these tools on a time-based software license, Thalia will also offer a design optimisation service directly and through partners.

By Nick Flaherty
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Wednesday, April 30, 2014

Heartbleed challenges the Internet of Things

"The Heartbleed security bug is a key example of the fundamental security challenge for the Internet of Things says Green Hills Software as it launches a new security group."

Heartbleed challenges the Internet of Things

 By Nick Flaherty

Wednesday, April 09, 2014

ARM moves to LLVM open source for future compilers

ARM is moving its future compilers to open source under the LLVM license in a fundamental shift away from proprietary technology.

ARM Compiler 6 supports the coming 64bit ARMv8 architecture and will be integrated into future versions of the DS-5 development suite for high and system on chip development. This will also become the basis of the compiler for microcontroller projects.
"The benefit for our users is greater feature velocity from open source," said Daniel Owens, product manager for software development tools at ARM. "The ARM v8 backend is in open source today as it goes into open source first, then we pull it back in for integration and testing in DS-5. V8 will be supported out of the gate and then V7A and R and that will happen by the end of this year and then following on is V7M and that's probably 2015 so Keil will stay with V7 through that time, he said.

More on this story at ARM moves to LLVM open source for future compilers - Electronics Eetimes

By Nick Flaherty

Tuesday, March 04, 2014

Bristol startup slashes memory power with standard logic process

Bristol startup slashes memory power with standard logic process:

 By Nick Flaherty

A Bristol startup has developed an entirely new way of building static memory on a standard logic process that cuts the power in half without paying a penalty in area or speed.
Rob Beat (L) and Mark de Souza
Rob Beat (L) and Mark de Souza
Silicon Basis is based at the EngineShed and is developing the tools to help chip designers add memory to their devices in a way that uses less power, reduces the number of extra chips they need and gives them flexibility to move to different process technologies.
“Fundamentally memory has some real problems everyone does it the same way,” said Mark de Souza, chief executive at Silicon Basis  and formerly at memory IP supplier Virage Logic. “They all take the TSMC arrays and put them together.” These arrays are specifically designed on a particular process.
Silicon Basis sees two key advantages for its technology it can save up to 50% of the power consumption and it can go below the bit cell voltage of the foundry memories. This lower voltage allows the memories to be powered by the same voltage source as the logic and so eliminates the need for a second DC-DC converter which adds cost and complexity to a design.
This also makes the technology foundry independent and scalable to new technologies such as FinFet, says de Souza. The company has produced all the models needed and is now working on 28nm silicon to prove the implementation.”We use our own bit cell so we are not restricted to the foundry’s Vmin which is a huge advantage,” said de Souza. “Dropping the voltage makes a huge difference.”
All of this comes from a new way of looking at the design of the cell which is currently being patented. “No one has seen this way of designing SRAM before,” he said. “We are talking to the experts in memory design and no one has seen this way of putting memory together. Its all using standard rules and standard CMOS. Its an architectural difference that means we don’t need to use sense amps and because we are using logic rules we can go down to the logic voltage floor and possibly below that.”
“Our cell size is about the same as the high speed cell from the foundry,” said Rob Beat, founder and chief technology officer of Silicon Basis and designer of the new cell. “There’s a compromise on area in the array but because the periphery is more efficient we are competitive in area especially on the smaller RAMs.”
The architecture brings advantages with the compiler that are not to be underestimated, he says. “Our single port compiler also outputs a one port register file,” he said. “Because of the way the bit cell is designed we can use the same bit cell for dual port so the dual port compiler will do the dual port register file and asynchronous dual port memory.” This avoids the problems of having up to five different compilers for each process technology with a significant support burden
The technology has been developed for the TSMC 40nm node and outperforms the high speed bit cell, says de Souza. “This took us a little bit by surprise as we didnt design for speed,” he said. “We did a lot of work at 40nm but what we are seeing from customers is that 28nm HPM is going to be a major node and we think there will be more new designs starting on 28nm than on 40nm.”
The technology is also fully compatible with FinFet vertical structures being used in TSMCs 16nm process node. “Our technology will work very nicely with FinFet right out of the box,” he said. 
The technology has previously been used by Beat to develop low power FPGA fabric but has attracted more interest for the SRAM compiler. “For me, Silicon Basis starts here,” said de Souza.

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