Thursday, April 20, 2017

Xilinx pushes dynamic reconfiguration technology

By Nick Flaherty

Being able to add new hardware to a design in the field just with a software download is one of the huge advantages of using a field programmable gate array (FPGA). Being able to do this for one element of the design without impacting on the rest - partial reconfiguration - is a key capability that has been many years coming.

Now the latest update of the Vivado design tool from leading FPGA maker Xilinx has included Partial Reconfiguration technology. This enables dynamic field updates and increased systems integration in a broad range of applications such as wired & wireless networking, test & measurement, aerospace & defense, automotive, and data centres. 

Designers can now change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility of All Programmable devices. System upgradeability & reliability are greatly enhanced by providing the ability to update feature sets in deployed systems, fix bugs, and migrate to new standards while critical functions remain active.

“The use of Partial Reconfiguration in Xilinx devices allowed us to optimize the size of the FPGA, and provide complete flexibility to maintain system connectivity while independently reconfiguring multiple ports in our design,” said Craig Palmer, senior engineering manager, Viavi Solutions.

The Partial Reconfiguration technology enables dynamic configurability by swapping portions of the design while the rest remains operational, requiring zero downtime and little impact to cost or development time.

“Partial Reconfiguration of FPGAs is a key element in Keysight’s toolbox for creating the next generation of test and measurement solutions. Partial Reconfiguration enables us to manage the ever increasing need for flexibility and complexity of test systems,” said Tom Vandeplas, senior researcherat test equipment maker Keysight Laboratories.

The Vivado Design Suite HLx Editions 2017.1 release is now available for download. Partial Reconfiguration functionality is now included at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK Edition at a reduced price. 

Wednesday, April 19, 2017

Researchers find flaws in RISC-V core

By Nick Flaherty

Researchers at Princeton University have found a number of significant flaws in the RISC-V open source processor core. The specification is set to come to market later this year, although some companies such as SiFive are already using it.  

The researchers, testing a technique they created for analyzing computer memory use, found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. Officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.

"Incorrect memory access orderings can result in software performing calculations using the wrong values," said Margaret Martonosi, Professor of Computer Science at Princeton and the leader of the Princeton team that also includes Ph.D. students Caroline Trippel and Yatin Manerkar. "These in turn can lead to hard-to-debug software errors that either cause the software to crash or to be vulnerable to security exploits. With RISC-V processors often envisioned as control processors for real-world physical devices (i.e., internet of things devices) these errors can cause unreliability or security vulnerabilities affecting the overall safety of the systems."

Krste Asanović, the chair of the RISC-V Foundation, welcomed the researchers' contributions. He said the RISC-V Foundation has formed a working group, headed by Martonosi's former graduate student and co-researcher Daniel Lustig, to solve the memory-ordering problems. Asanović, a professor of electrical engineering and computer science at the University of California-Berkeley, said the RISC-V project was looking for input from the design community to "fill the gaps and the holes and getting a spec that everyone can agree on."

"The goal is to ratify the spec in 2017," he said. "The memory model is part of that."

Lustig, a co-author of Martonosi's recent paper and now a research scientist at NVIDIA, said work was underway to improve the RISC-V memory model.

"RISC-V is in the fortunate position of being able to look back on decades' worth of industry and academic experience," he said. "It will be able to learn from all of the insights and mistakes made by previous attempts."

The RISC-V instruction set was first developed at UC-Berkeley, with the idea that any designer could use the instruction set to create processor cores and software compilers. The project is now run by the RISC-V Foundation, whose membership includes a roster of universities, nonprofit organizations and top technology companies, including Google, IBM, Microsoft, NVIDIA and Oracle.

Martonosi's team discovered the problems when testing their new system to check memory operations across any computer architecture. The system, called TriCheck, allows designers and others interested in working with a design, to detect memory ordering errors before they become a problem. The tool has three general levels of computing: the high-level programs that create modern applications from web browsers to word processors; the instruction set architecture that functions as a basic language of the machine; and the underlying hardware implementation, a particular microprocessor designed to execute the instruction set.

The memory ordering challenge stems from the complexity of modern computers. As designers squeeze more performance out of computer systems, they rely on many concurrent operations sharing the same sections of computer memory. This parallel, shared-memory operation is extremely efficient, both for speed and power usage, but it puts a heavy demand on the computer's ability to interleave and properly order memory usage. If, for example, several processes are using the same section of memory, the computer needs to make sure that operations are applied to memory in the correct order, which may not always be the order in which they arrive from different concurrently running processors.

Subtle changes in any of the three computing levels — the machine level, the compiler and the high-level programming languages — can have unintended effects on the other layers. All three have to work together seamlessly to make sure memory errors don't crop up. One advantage of TriCheck is that it allows experts in one of these layers to avoid conflicts with the other two layers, even if they do not have expertise in them.

"If I write a program in C, it makes some assumptions about memory ordering," said Martonosi. "Subsequently, a different set of memory ordering rules are defined by the instruction-set architecture. We need to check that the high-level program's assumptions are accurately supported by the underlying instruction set and processor design."

However, the researchers said the TriCheck's greatest strength is its ability to give designers a broad view of memory usage. Although designers have long been interested in this perspective, previous attempts to comprehensively analyze memory operations have been too slow to be practical.

TriCheck is able to check memory ordering efficiently by using succinct formal specifications of memory ordering rules, known as axioms. For a given program, compiler, instruction set and hardware implementation, TriCheck can enumerate many ordering possibilities from these axioms, and then check for errors. By expressing the memory-ordering possibilities as connected graphs, TriCheck can identify potential errors by looking for cycles in the graphs. These checks can be done very efficiently on modern high-performance computers, and TriCheck's speed has allowed it to explore larger and more complex designs than prior work. 

"TriCheck is an important step in our overall goal of verifying correct memory orderings comprehensively across complex hardware and software systems," she said. "Given the increased reliance on computer systems everywhere — including finance, automobiles and industrial control systems — moving towards verifiably correct operation is important for their reliability and safety."

The TriCheck project culminates four years of work by Martonosi's group of developing checks across various layers of hardware, memory and software.

Other stories:

Friday, April 14, 2017

Actility raises $75m for wide area IoT

By Nick Flaherty

French low power wide area network (LPWAN) technology developer Actility has raised $75m to expand its delivery of the industrial Internet of Things (IoT) using a wide range of technologies .

The Series D funding round included Creadev, Bosch and Inmarsat, alongside telecoms operators KPN, Orange Digital Ventures, Swisscom and equipment maker Foxconn. A second closing later this month will see additional strategic investors joining the company without involving banks.

Actility's ThingPark platform is used for large-scale LPWA rollouts worldwide with the LoRaWAN LPWAN protocol that Actility co-developed, as well as LTE-M and NB-IoT. A software stack with the OS service and business support manager, application integration enabler, and e-commerce platform provides a turn-key IoT platform supporting sensor to cloud applications.

“This funding will enable us to grow our IoT technology and ecosystem platform faster to meet the needs of service providers, solution providers and enterprises in large industry verticals, for example rolling out our disruptive global location and tracking service more quickly,” said Actility CEO Mike Mulica. “It will also allow us to accelerate our strategy for the US, and build strength in China. And last but by no means least, it will enable us to look at strategic acquisitions to broaden our technology portfolio and cement our leadership in LPWA.”

“We have been looking the best project in the business of connectivity for the IoT for a while," said Florent Thomann, a member of Creadev’s management board, and in charge of new digital models. "In Actility, we found a company that offers an ideal solution and has made the perfect technology choices in LPWA and LTE-M to meet that growing connectivity market. We are convinced by both the company and its management, which shows a real visionary insight into the technology and business models and the way that connectivity will evolve. Furthermore, Actility’s team is proving to be particularly agile at innovation, adapting to new technologies very efficiently. We are pleased to bring our culture of ambition, support and sharing best business practice to help nurture Actility’s long-term growth.”

Having a satellite operator such as Inmarsat is a significant boost. “Inmarsat sees a great deal of potential in Actility, and its expertise in global IoT networks, based on LoRaWAN, makes it a natural fit for our investment," said Paul Gudonis, President of Inmarsat Enterprise. "There are clear synergies between us, namely the ability to deliver innovative connectivity services to customers in remote locations, creating the potential for a global IoT network. To this end, we recently developed our LoRaWAN-based network in partnership with Actility to enable IoT to reach every corner of the globe. We have many more projects planned with Actility and we are excited to support the company’s rapid growth as it continues to make great strides in the IoT arena. This market is rapidly maturing and Actility, with its growing ecosystem of partners, is ideally positioned to take advantage of this for the benefit of businesses across a variety of industries.”

Related stories: 

Friday, April 07, 2017

Cognex buys machine learning developer for vision systems

US machine vision giant Cognex has bought a Swiss developer of machine learning software, highlighting the increasing interest in artificial intelligence in embedded systems.

ViDi Systems, based in Villaz-St.-Pierre, Switzerland, was founded in 2012 by computational neuroscientist Dr Reto Wyss and the CPA Group, a Swiss industrial holding company and business incubator. This follows two machine vision acquistion late last year.

ViDi’s deep learning software uses artificial intelligence techniques to improve image analysis in applications where it is difficult to predict the full range of image variations that might be encountered. Using feedback, ViDi’s software trains the system to distinguish between acceptable variations and defects.

EnShape in Jena, Germany, was acquired in October for its patented 3D area-scan technology for fast image capture at high resolution, and eliminate the need to mechanically move objects in front of the device as required with laser line scanners. This created a new Cognex engineering centre in Jena.

In August Cognex also completed the acquisition of 3D vision software developer AQSense in Girona, Spain. AQSense develops and sells a library of field-tested 3D vision tools, and the company’s software engineers joined Cognex’s 3D engineering team upon the closing of the acquisition.

The story is here: Cognex continues European buying spree with machine learning developer

By Nick Flaherty

Related stories:

Thursday, April 06, 2017

NXP combines Kinetis and LPC development tools

By Nick Flaherty

NXP has combined the development tools for two of the most popular embedded microcontrollers in the industry, giving designers dramatically more flexibility in system implementation.

The MCUXpresso Integrated Development Environment (IDE) unifies development support for thousands of LPC and Kinetis (formerly Freescale) MCUs based on ARM Cortex-M cores using the same software suite.

The MCUXpresso IDE features simple, scalable and user-friendly interfaces and tools and is built to leverage the capabilities of the highly popular MCUXpresso SDK and Config Tools. The new feature-rich, Eclipse-based framework completes the trio of powerful MCUXpresso software development solutions and provides access to thousands of new project wizards and clone projects, saving designers valuable time by giving them a head-start to customise their own innovations.

“If design tools are simple, yet comprehensive, our customers stand a much better chance of designing tomorrow’s next amazing innovation,” said Geoff Lees, senior vice president and general manager of the microcontroller business line at NXP. “This unified software enablement gives developers more choice in high-quality controller solutions to fit their design needs. NXP will continue to stay ahead of the design trends and expand our MCUXpresso software and tools to support a variety of products in the future, ensuring our customers have access to the most comprehensive design tools on the market.”

Available in full-featured free and professional upgrade editions, the MCUXpresso IDE unifies Kinetis and LPC microcontrollers under a set of compatible tools. With a dedicated quickstart panel, automatic probe detection and configuration, and an intuitive project creation and cloning wizards, the MCUXpresso IDE is designed to ease developers through the setup and optimisation of their projects to application design and even multicore development. The MCUXpresso IDE supports full-featured, advanced debugging with unlimited code size and code profiling in the free offering, adds advanced trace features in the professional edition, and preserves hardware investments by supporting the former Freescale Freedom and Tower System, as well as LPCXpresso boards and custom hardware platforms.

This MCUXpresso SDK release adds new device support and includes examples and project files for use in the new MCUXpresso IDE. The MCUXpresso SDK also now includes support for NXP’s NTAG I2C Plus connected NFC tag for home-automation and consumer applications and will soon support the FRDM-KW41Z board designed for portable, extremely low power applications requiring Bluetooth® low energy (BLE) v4.2 and IEEE 802.15.4 RF connectivity. The MCUXpresso Config Tools offers a single powerful configuration environment with pins and clocks tool for dynamic generation of initialisation C code, and quickly guides users to example projects and web-based tools for rapid board bring-up.

Related stories:

Wednesday, April 05, 2017

Intel McAfee security deal is all about the IoT this time

By Nick Flaherty

Intel buying McAfee in 2011 for $7.7bn was all about the enterprise. Now, Intel spinning out McAfee into a separate company in a $4.2bn deal that is all about the Internet of Things.
Back in 2011, Intel was aiming to secure the enterprise alongside its PC and server processors in a market where it dominated. Now it needs to secure the IoT, it needs cooperation from companies that license the ARM architecture. Hence the need for an independent venture.
The key change is the McAfee Data Exchange Layer (DXL), the industry-endorsed communication fabric providing real-time interaction between applications. This needs to be taken down the stack to the gateway, where Intel processors are being used, but further down to the node. This is the challenge. Another Intel company, Wind River, is already taking up that challenge, pushing the VxWorks real time operating system further into the IoT.
The McAfee Security Innovation Alliance has over 135 partners around the world, and 30 of these are using the DXL connection as an API.
The giveaway is in the new strapline for McAfee - innovation, trust, and collaboration. The new company is 49% owned by Intel, with the remainder from equity house TPG and private equity investment firm Thoma Bravo, bu tit has to demonstrate that it can work well with the rest of the industry that does not rely on Intel. Intel Senior Vice President and General Manager Chris Young will lead the new McAfee as Chief Executive Officer. TPG partner Bryan Taylor has been named Chairman of the Board.
“Cybersecurity is the greatest challenge of the connected age, weighing heavily on the minds of parents, executives and world leaders alike,” said Christopher Young, CEO of McAfee. “As a standalone company with a clear purpose, McAfee gains the agility to unite people, technology and organizations against our common adversaries and ensure our technology-driven future is safe.”
“We offer Chris Young and the McAfee team our full support as they establish themselves as one of the largest pure-play cybersecurity companies in the industry,” said Brian Krzanich, CEO of Intel. “Security remains important to Intel, and in addition to our equity position and ongoing collaboration with McAfee, Intel will continue to integrate industry-leading security and privacy capabilities in our products from the cloud to billions of smart, connected computing devices.”
The advantage of DXL is that it is an open standard. Unlike typical integrations, each application connects to the universal DXL communication fabric and there is just one integration process instead of multiple efforts, which makes it suitable for enterprise scale IoT deployments.
OpenDXL will support a broad range of languages, enabling developers to create integrations using their favourite development environment. One app publishes a message or calls a service; one or more apps consume the message or respond to the service request.
As is the goal for any standard, the interaction is independent of the underlying proprietary architecture of each integrating technology and integrations are much simpler because of this abstraction from vendor-specific APIs and requirements.
In addition to creating native DXL integrations, developers can also wrap their services to interact or wrap the API of a commercial product to publish data onto DXL. Other services can listen to DXL messages and calls to enrich their functionality with the latest data, or take appropriate action. For a more sophisticated app reflecting orchestration, these sorts of actions can be scripted together to drive a waterfall—or simultaneous set—of actions.

The challenge now is to persuade the wider embedded industry that the new McAfee is truly independent of Intel in order to use the technology.

Related stories on the Embedded Blog: 

Tuesday, April 04, 2017

SYSGO optimizes multicore support and energy efficiency in PikeOS 4.2

By Nick Flaherty

SYSGO has optimized its PikeOS hard real time operating system for multicore designs with a hypervisor and separation microkernel.

Release 4.2 has been designed specifically for systems and applications that need certification according to safety or security standards such as DO-178B/C, EN 50128, ISO 26262, as well as Airbus SAR and Common Criteria requirements.

A fine granular kernel locking that enables all cores to continue their processes even while one of them executes a system call, greatly reducing unproductive processor cycles. Other cores may only be blocked, if they attempt to access the exact same resource in order to control interference. This is necessary for the latest ARINC-653 multicore standard.

PikeOS 4.2 also improves the energy efficiency of embedded systems as it allows the developer to manage multiple hardware clock devices and frequencies on the same board - including System on Chip (SoC) internal and external clocks. This way, applications as well as IPs on the SoC can easily be stopped and restarted as needed, reducing both resource and energy consumption.

PikeOS 4.2 provides a modern compact and certifiable Hypervisor technology with separation microkernel, implementing robust time and resource partitioning, which allows interference channels to be managed within your certifiable project. In addition, PikeOS 4.2 provides time schedules for individual resource partitions by core, where direct CPU affinity may be used to implement core separation for ultra critical partitions to be managed with PikeOS.
"Being the leading European operating system manufacturer, we have a long track record in supporting our customers in the entire certification process", said SYSGO's VP of Marketing & Product Strategy, Franz Walkembach. "With PikeOS 4.2, these customers have now access to a software platform that has been strictly designed with certification in mind. What is more – they will also benefit from an entire ecosystem around this platform which brings together the expertise of SYSGO, our partners and the scientific community."

PikeOS 4.2 will be available this month for multicore CPUs, including ARM v7 and v8, 32 and 64 bit PowerPC and 32 and 64 bit x86. Board Support Packages (BSPs) are available for a wide selection of silicon vendors like NXP/Freescale, Renesas, Intel, Xilinx and Altera.

The first product based on PikeOS 4.2 will be SYSGO’s own safety and security certification kit that will enable customers an efficient safety or security certification kick-off element. Therefore helping to reduce time spent during long certification programmes.

Monday, April 03, 2017

Top stories in March

By Nick Flaherty

The cloud and AI have dominated stories on the Embedded blog in March.While security concerns for the Internet of Things are still dominant,from a low cost encryption chip and ways to hcck smartphone using their accelerometers, edge analytics (with VxWorks) and ARM chips being using in  Microsoft's Azure cloud were more prominent, as well as NVIDIA's Jetson 2 embedded card for artificial intelligence.


Power news this week


Europe's largest supercapacitor factory opens
.Europe's largest supercapacitor factory opens
MaxLinear buys Exar in $700m deal
.MaxLinear buys Exar in $700m deal
High efficiency thin film perovskite solar cell patent granted to Solar-Tectic
.High efficiency thin film perovskite solar cell patent granted to Solar-Tectic


New nanomaterials promise improved harvesting, storage of sunlight
.New nanomaterials promise improved harvesting, storage of sunlight
Thermoelectric modules take over 1-million temperature cycles
.Thermoelectric modules take over 1-million temperature cycles
Wireless chargers target materials handling
.Wireless chargers target materials handling


Single-chip digitally enhanced power targets DC-DC converters
.Single-chip digitally enhanced power targets DC-DC converters
PMIC reduces cuts footprint of wearable medical and fitness design in half
.PMIC reduces cuts footprint of wearable medical and fitness design in half


Laird: Thermal Management for Semiconductor Metrology Equipment
.Laird: Thermal Management for Semiconductor Metrology Equipment
CUI: How to Stay Ahead of Efficiency Regulations for Power Adapters
.CUI: How to Stay Ahead of Efficiency Regulations for Power Adapters


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