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Thursday, May 23, 2019

Superconductivity moves towards room temperature

By Nick Flaherty www.flaherty.co.uk

Researchers in the US have shown superconductivity at the highest temperatures ever recorded.

The team at the Argonne National Laboratory found a material with superconductivity at temperatures of about -23 degrees Centigrade, a jump of about 50 degrees compared to the previous confirmed record.

Though the superconductivity happened under extremely high pressure, the result still represents a big step toward creating superconductivity at room temperature--the ultimate goal for scientists to be able to use this phenomenon for advanced technologies. 

Just as a copper wire conducts electricity better than a rubber tube, certain kinds of materials are better at becoming superconductive, a state defined by two main properties: The material offers zero resistance to electrical current and cannot be penetrated by magnetic fields. The potential uses for this are as vast as they are exciting: electrical wires without diminishing currents, extremely fast supercomputers and efficient magnetic levitation trains.

Recent theoretical predictions have shown that a new class of materials of superconducting hydrides could pave the way for higher-temperature superconductivity. Researchers at the Max Planck Institute for Chemistry in Germany teamed up with University of Chicago researchers to create one of these materials, called lanthanum superhydrides, test its superconductivity, and determine its structure and composition.

The only catch was that the material needed to be placed under extremely high pressure--between 150 and 170 gigapascals, more than one and a half million times the pressure at sea level. Only under these high-pressure conditions did the material--a tiny sample only a few microns across--exhibit superconductivity at the new record temperature.

The material showed three of the four characteristics needed to prove superconductivity: It dropped its electrical resistance, decreased its critical temperature under an external magnetic field and showed a temperature change when some elements were replaced with different isotopes. The fourth characteristic, called the Meissner effect, in which the material expels any magnetic field, was not detected. That's because the material is so small that this effect could not be observed, researchers said.

They used the Advanced Photon Source at Argonne National Laboratory, which provides ultra-bright, high-energy X-ray beams that have enabled breakthroughs in everything from better batteries to understanding the Earth's deep interior, to analyze the material. In the experiment, researchers within University of Chicago's Center for Advanced Radiation Sources squeezed a tiny sample of the material between two tiny diamonds to exert the pressure needed, then used the beamline's X-rays to probe its structure and composition.

Because the temperatures used to conduct the experiment is within the normal range of many places in the world, that makes the ultimate goal of room temperature--or at least 0 degrees Celsius--seem within reach.

Tuesday, May 21, 2019

Achronix turns to network-on-chip for AI accelerators in 7nm FPGA

By Nick Flaherty www.flaherty.co.uk

Achronix Semiconductor has launched its latest FPGA family aimed at artificial intelligence, machine learning and high-bandwidth data acceleration applications. 

The Achronix Speedster7t family is based on a new architecture that is optimised for high-bandwidth workloads with a 2D network-on-chip (NoC), and a high-density array of new machine learning processors (MLPs) blocks optimised for high-bandwidth and AI/ML workloads. This blending of FPGA programmability and ASIC routing structures and compute engines boosts performance.

“The growth potential for AI/ML is astounding, and the use cases are rapidly evolving, and we are offering a new solution to address the varying requirements of high performance, flexibility and time to market,” said Robert Blake, president and CEO of Achronix Semiconductor. “Our Speedster7t family breaks new ground as the first solution to deliver FPGA adaptability with ASIC-like performance. We believe our new ‘FPGA+’ class of technology truly pushes the boundaries in the high-performance market.”
Manufactured on TSMC’s 7nm FinFET process, Speedster7t devices are designed to accept massive amounts of data from multiple high-speed sources, distribute that data to programmable on-chip algorithmic and processing units, and then deliver those results with the lowest possible latency. They include high-bandwidth GDDR6 interfaces, 400G Ethernet ports, and PCI Express Gen5 — all interconnected to deliver ASIC-level bandwidth while retaining the full programmability of FPGAs.

“The new Achronix Speedster7t FPGA family is a prime example of the explosion of innovative silicon architectures created to handle massive amounts of data that are aimed directly at AI applications”, said Rich Wawrzyniak, principal market analyst for ASIC and SoC at Semico Research Corp. “Combining math functions, memory and programmability into their machine learning processor, combined with the cross chip, two-dimensional NOC structure, is a brilliant method of eliminating bottlenecks and ensuring the free flow of data throughout the device. In AI/ML applications, memory bandwidth is everything and the Achronix Speedster7t delivers impressive performance metrics in this area.” Semico’s forecast shows the market size for FPGAs in AI applications will grow by 3x in the next four years to over $4.8B.

The massively parallel array of programmable compute elements within the new machine learning processors (MLPs) are highly configurable, compute-intensive blocks that support integer formats from 4 to 24 bits and efficient floating-point modes including direct support for TensorFlow’s 16-bit format as well as a block floating-point format that doubles the compute engines per MLP.

The MLPs are tightly coupled with embedded memory blocks, eliminating the traditional delays associated with FPGA routing to ensure that data is delivered to the MLPs at the maximum performance of 750 MHz. This combination of high-density compute and high-performance data delivery results in a processor fabric that delivers the highest usable FPGA-based tera- operations (TOps) per second.

The family includes GDDR6 high speed memory controllers capable of supporting 512 Gbps of bandwidth, the up to 8 GDDR6 controllers in a Speedster7t device can support an aggregate GDDR6 bandwidth of 4 Tbps, delivering the equivalent memory bandwidth of an HBM-based FPGA at a fraction of the cost.

Along with this memory bandwidth, Speedster7t devices include the industry’s highest performance interface ports to support extremely high-bandwidth data streams. Speedster7t devices have up to 72 of the industry’s highest performance SerDes that can operate from 1 to 112 Gbps plus hard 400G Ethernet MACs with forward error correction (FEC), supporting 4x 100G and 8x 50G configurations, plus hard PCI Express Gen5 controllers with 8 or 16 lanes per controller.

The 2D NoC spans horizontally and vertically over the FPGA fabric, connecting to all of the FPGA’s high-speed data and memory interfaces. Each row or column in the NoC is implemented as two 256-bit, unidirectional industry-standard AXI channels operating at 2 GHz, delivering 512 Gbps of data traffic in each direction simultaneously.

Most importantly, the NoC eliminates the congestion and performance bottlenecks that occur in traditional FPGAs that use the programmable routing and logic lookup table (LUT) resources to move data streams throughout the FPGA. This high-performance network not only increases the overall bandwidth capacity of Speedster7t FPGAs, but also increases the effective LUT capacity while reducing power.

The FPGAs include bitstream security features with multiple layers of defence for protecting bitstream secrecy and integrity. Keys are encrypted based on a tamper-resistant physically unclonable function (PUF), and bitstreams are encrypted and authenticated by 256-bit AES-GCM. To defend against side-channel attacks, bitstreams are segmented, with separately derived keys are used for each segment, and the decryption hardware employs differential power analysis (DPA) counter measures. A 2048-bit RSA public key authentication protocol is used to activate the decryption and authentication hardware. 

The Speedster7t FPGA devices range from 363K to 2.6M 6-input LUTs. The first devices and development boards for evaluation will be available in Q4 2019. 



Monday, May 13, 2019

Siemens $30bn power spinout ... $1bn SiC boost at Cree ... Integrating sensors onto a GaN power chip ... first defect free 2in AlN wafer

Power news this week by Nick Flaherty at eeNews Europe Power www.flaherty.co.uk

. Siemens spinout to create $30bn power giant


. Romeo teams with BorgWarner for battery cell and pack production


. $1bn silicon carbide boost at Cree

POWER TECH TO WATCH
. X-Fab teams for first substrate analysis tool for high voltage designs

. GaN single chip integrates sensors for the first time

. First defect-free AlN power wafer

NEW POWER PRODUCTS

. 1200V IGBT family reduces automotive inverter size

. Three pin packages boost 650V silicon carbide FETS

. Power density boost of 48x from new 8x8mm package

TECHNICAL PAPERS
. Using precision current sensing to optimize system performance


. Infineon: Semiconductor solutions for robotics

Top 29 IoT companies in 2019 by Frost & Sullivan

By Nick Flaherty www.flaherty.co.uk

With over 60 billion connected devices expected globally by 2024, the Internet of Things (IoT) is a complex ecosystem that integrates Information technology (IT) with operations technology (OT) to generate data that can be analyzed to increase revenues and improve business productivity.

IoT platforms are the building blocks of IoT solutions, offering multiple services such as application enablement, device management, and connectivity management, and we have covered a wide range of thises as a key element in embedded designs.

Market researchers Frost & Sullivan looked at 1,000 platforms around the world, chose 400 that true platform capabilities across multiple vertical markets and consumer segments. It then selected 29 that are at the cutting edge of innovation and growth in this highly fragmented market.

These are: 

AWS, ARM, AT&T, Ayla Networks, Bosch, C3IoT, Carriots, Cisco Jasper, Dell/EMC, Eurotech, GE, Google, HPE, Hitachi, Huawei, IBM, Intel, Losant, Microsoft, Oracle, Salesforce, Samsung, SAP, Siemens, Software AG, ThingWorx, Verizon, Vodafone, and Telit.


The figure shows the positioning of each platform, with AWS and Microsoft seeing the highest growth.

“Companies will gain an objective, independent perspective of their innovation and growth strategies, including their robustness, effectiveness, and relative competitive strength, as well as implications on their long-term success,” said Dilip Sarangan, IoT Global Program Manager at Frost & Sullivan.

http://frost.ly/3fr

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Thursday, May 09, 2019

PikeOS hypervisor certified for IEC61508 safety and security

By Nick Flaherty www.flaherty.co.uk

SYSGO has been awarded key safety and security certifications for its hypervisor that runs on the PikeOS real time operating system.

The certifications will be a boost fo SYSGO following the acquisition of competing RTOS vendor Express Logic by Microsoft.
According to TÜV Süd, the hypervisor meets the requirements of Safety Integrity Level 2 of the IEC 61508 for safety-relevant electrical and electronic systems. TÜV Süd also certifies compliance with SIL 2 for the railway-specific standard DIN EN 50128. In the automotive industry, it is certified as a SEooC (Safety Element Out Of Context) to ASIL B (Automotive Safety Integrity Level), as defined in the ISO 26262 standard. All certifications refer to PikeOS version 4.2.3 (S5577) for the target architectures X86-AMD 64bit, ARMv7 and ARMv8.

Security certification to Common Criteria EAL 3+ for PikeOS 4.2.3 (S5577) was published by the Federal Office for Information Security (BSI) during a maintenance procedure. The most recent version was certified following an upstream analysis of critical points in an independent testing laboratory, taking over essential certification artefacts of the previous version PikeOS 4.2.2.

"Not only the safety certification but also the renewed security CC-certification by BSI emphasizes our path to provide customers with a reliable platform for certifiable applications in the most critical environments," said Sven Nordhoff, Director Certification at SYSGO. "In doing so, the architecture of PikeOS is designed to support the most stringent safety and security standards across all industries." 

The current version 4.2 of PikeOS focus on "medium"-critical projects but the roadmap is aiming for safety and security standards up to DO-178C DAL A, EN50128/IEC61508 SIL 4 and ISO 26262 ASIL D.  "We are actively involved in standardization initiatives, identify technological trends at an early stage and enabling us to quickly embrace evolving standards," said Nordhoff.


Mini-ITX board has 14nm Coffee Lake six core processor

By Nick Flaherty www.flaherty.co.uk

Dutch board maker Portwell has launched a Mini-ITX form factor embedded system board based on Intel's 14nm 8th Generation Intel Core processor known as Coffee Lake and Intel Q370 Express chipset. 

With four independent video outputs, the WADE-8211 also includes Intel's Turbo Boost Technology for faster processing, vPro Technology for remote configuration and Hyper-threading for multithreaded processing. These translate into reduced manageability cost and improved security in industrial automation, medical equipment, transportation and retail systems.
The Q370 Express chipset provides 2x GbE LAN and BIOS configurable PCI Express Lanes and the board is tested for enhanced operating temperature range up to 60°C and 24/7 continuous operation. It supports up to 32GB Non-ECC DDR4 memory up to 2133MHz on two 260-pin SO-DIMM sockets making it faster than its predecessor. 

The expansion interface supports one PCI Express x16 Gen3 (8.0GT/s) for enhanced video performance and support one Mini-PCIe and two M.2 slots (one M.2 Type E socket (2230) for Wireless, one M.2 Type M socket (2242/2260/2280) for SSD).

The board can support four types of independent displays, dual DP (Display Port), VGA and 24bit LVDS with greater 3D performance compared to its previous generation and runs with a low TDP CPU of 35W.

Wednesday, May 01, 2019

3D printing flexible circuits

By Nick Flaherty www.flaherty.co.uk


Example of a flexible and transparent electronic component: a flexible capacitor. Credit: University of Hamburg, Tomke Glier

Researchers at the University of Hamburg and DESY has developed a process suitable for 3D printing that can be used to produce transparent and mechanically flexible electronic circuits.

The electronics consists of a mesh of silver nanowires that can be printed in suspension and embedded in various flexible and transparent plastics (polymers). This technology can enable new applications such as printable light-emitting diodes, solar cells or tools with integrated circuits. The researchers are demonstrating the potential of their process with a flexible capacitor, among other things.

“The aim of this study was to functionalize 3D-printable polymers for different applications,” said Michael Rübhausen from the Centre for Free-Electron Laser Science (CFEL), a cooperation between DESY, the University of Hamburg and the Max Planck Society. 

“With our novel approach, we want to integrate electronics into existing structural units and improve components in terms of space and weight.” Using the bright X-ray light from DESY's research light source PETRA III and other measuring methods, the team has precisely analyzed the properties of the nanowires in the polymer.
“At the heart of the technology are silver nanowires, which form a conductive mesh,” said Glier. The silver wires are typically several tens of nanometers thick and 10 to 20 microns long. The detailed X-ray analysis shows that the structure of the nanowires in the polymer is not changed, but that the conductivity of the mesh even improves thanks to the compression by the polymer, as the polymer contracts during the curing process.

The silver nanowires are applied to a substrate in suspension and dried. “For cost reasons, the aim is to achieve the highest possible conductivity with as few nanowires as possible. This also increases the transparency of the material,” said Roth, head of the P03 measuring station at DESY's X-ray light source PETRA III, where the X-ray investigations took place. “In this way, layer by layer, a conductive path or surface can be produced.” A flexible polymer is applied to the conductive tracks, which in turn can be covered with conductive tracks and contacts. Depending on the geometry and material used, various electronic components can be printed in this way.

The researchers produced a flexible capacitor. “In the laboratory, we carried out the individual work steps in a layering process, but in practice they can later be completely transferred to a 3D printer,” said Glier. “However, the further development of conventional 3D printing technology, which is usually optimized for individual printing inks, is also essential for this. In inkjet-based processes, the print nozzles could be clogged by the nanostructures,” said Rübhausen.

In the next step, the researchers now want to test how the structure of the conductive paths made of nanowires changes under mechanical stress. “How well does the wire mesh hold together during bending? How stable does the polymer remain,” said Roth, referring to typical questions. “X-ray investigation is very suitable for this because it is the only way we can look into the material and analyze the conductive paths and surfaces of the nanowires.”

Friday, April 26, 2019

SiFIve teams with QuickLogic for RISC-V templates with embedded AI

By Nick Flaherty www.flaherty.co.uk

RISC-V pioneer SiFive has teamed up with FPGA maker Quicklogic on a series of  SoC Templates that shorten the development time of system-on-chip devices with embedded artificial intelligence (AI) for a wide range of industrial and consumer applications.

For example, a Predictive Maintenance (PdM 4.0) template supports digital and analogue sensors used in Industry 4.0 predictive maintenance protocols. This template is optimized for power-efficient performance in industrial, automotive and AI and machine learning (ML) applications.

The Freedom Aware family of SoC Templates lowers the cost and development time associated with new SoC designs through the use of tested building blocks and a full suite of development tools that ensure finished SoCs mirror the results of pre-fabrication software emulations. 

Taking advantage of SoC Templates, users can greatly reduce the design cycle to only a few months, reduce the total cost to first silicon by an order of magnitude, and most importantly, provide custom silicon solutions while removing the dependency on large semiconductor design teams.

"We are extremely proud of our strategic partnership with SiFive and the role we are playing in the development of the industry's first family of SoC Templates," said Brian Faith, president and CEO of QuickLogic. "SoC Templates are what the industry needs to accelerate the development and introduction of the highly diverse products that are broadly referred to as the Internet of Things."

The templates are based around SiFive's heterogeneous multi-core architecture and QuickLogic's AI subsystem that is available with programmable acceleration and sophisticated power-management technology that delivers ultra-low power solutions optimized for battery-powered consumer and industrial IoT applications.

A template for an MCU for IoT is aimed at industrial and commercial IoT devices, featuring multiple processors, security cores, hardware accelerators and always-on sensing. Applications include consumer IoT, industrial IoT, and wearables.

The Always-on Voice Processor template is optimized for smart devices and mobile handsets, featuring multiple microphone processors and accelerators to enable superior far and near field, close talk and acoustic use cases. Applications include smart speakers, voice assistants, smart appliances and smartphones.

SiFive and QuickLogic are working with a number of potential customers via the FA Early Adopter program. Companies that join the Early Adopter program will have exclusive, early access to the Freedom Aware SoC Templates, the ability to add features and will be able to develop SoC designs that will be ready to launch next year.

"Our Core IP Series have driven greater intelligence at the edge. Now, with the new Freedom Aware family of SoC Templates, we are responding to the need for a complete, economical, and rapid time-to-market SoC solution," said Naveed Sherwani, president and CEO of SiFive. 

"Freedom Aware combines QuickLogic's IP and expertise in ultra-low-power SoC design with SiFive's leadership in RISC-V processing and design platforms to produce powerful and agile SoC Templates for the targeted applications. With these resources, and the sophisticated development tools that support them, we are opening vast new markets for innovation by democratizing SoC design."

www.sifive.com.

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Thursday, April 25, 2019

Adesto teams with IBM and NXP on IIoT security

By Nick Flaherty www.flaherty.co.uk

Adesto Technologies has teamed up with IBM and NXP Semiconductors on end-to-end security for smart buildings and the Industrial Internet of Things (IIoT).

Adesto's SmartServer IoT edge server and the IBM Watson IoT Platform, together enabled by NXP’s ready-to-use A71CH secure element for IoT devices, provide an extra layer of security for businesses connecting their systems securely to the IBM Cloud.

The SmartServer IoT simplifies the complexities of interoperability between legacy systems, disparate devices, and the numerous emerging and traditional protocols in industrial and building automation to enable seamless and secure access to data. It provides built-in device and data management for sensors, meters, actuators and controllers through a growing range of protocols including BACnet, LonWorks and Modbus.

NXP's A71CH is optimised for Watson IoT’ with a root of trust (RoT) at the chip level and delivers chip-to-cloud security right out of the box. Through integration with Adesto’s SmartServer IoT, it enables customers with additional security when connecting their buildings to IBM’s Watson IoT Platform without exposing keys for the lifetime of a device. 

This uses X.509 certificates and keys trusted by Watson IoT Platform and injected at NXP secure certified facilities. NXP’s trust provisioning service ensures keys are kept safe, and credentials are injected in a trusted environment. When embedded into devices, the chips have the necessary keys to establish a secure TLS connection with IBM Watson IoT enabling seamless device-to-cloud connections.

“While the IoT holds great promise, the connectivity of everything also creates significant vulnerabilities. Connected devices are potential targets for unauthorized network access, malicious control, and data theft,” said Philippe Dubois, vice president and general manager of IoT security at NXP Semiconductors. “We believe that IoT security must be silicon-based, and easy to implement. With the A71CH Plug & Trust Secure Element, we’re making it simple for customers to securely connect a plurality of air-gapped devices into the IBM public cloud.”

“IBM Watson IoT enables customers to maximize the value of their physical assets,” said Sanjay Tripathi, VP of strategy and business development, IBM IoT. “We are continuing to grow the ecosystem of enabling technologies around this platform to provide even greater value. By working with NXP to ensure its A71CH secure element is pre-loaded with the certificates needed to connect to IBM Watson IoT, we’re helping customers streamline their chip-to-cloud security and device onboarding. We are also working with Adesto to provide the critical connection from our customers’ industrial data to our platform. Through these relationships, we’re letting customers concentrate more fully on extracting the business value from their data.”


Zephyr launches its first stable IoT RTOS release

The Zephyr Project has introduced its first long term support (LTS) release of its real time operating system (RTOS) for the Internet of Things (IoT), Zephyr 1.14.0 LTS. This marks an important technical milestone for the community and is intended to be a more stable, certifiable option for product makers and developers. 

By Nick Flaherty www.flaherty.co.uk

The Zephyr project now supports over 160 different board configuration spanning 8 architectures. All architectures are rigorously tested and validated using one of the many simulation platforms supported by the project: QEMU, Renode, ARC Simulator, and the native POSIX configuration.
It adds UART, USB, and display drivers to the native POSIX port, and based on this port, the developers added a simulated NRF52832 SoC which enables running full system, multi-node simulations, without the need of real hardware.

MISRA-C code guidelines were used  on the kernel and core components of Zephyr to improve code safety, security and portability, and an experimental BLE split software Controller with Upper Link Layer and Lower Link Layers has been added for supporting multiple BLE radio hardware architectures.
Zephyr now has support for the x86_64 architecture. It is currently implemented only for QEMU targets, supports arbitrary numbers of CPUs, and runs in SMP mode by default, our first platform to do so. There is also added support for application user mode, application memory partitions, and hardware stack protection in ARMv8m.

An overhaul of the network packet net-pkt API means the majority of components and protocols now use the BSD socket API for IoT applications via MQTT, CoAP, LWM2M, and SNTP.
The power management subsystem has also been overhauled to support device idle power management and move most of the power management logic from the application back to the BSP.

The timing subsystem has been reworked and reimplemented, greatly simplifying the resulting drivers, removing thousands of lines of code, and reducing a typical kernel build size by hundreds of bytes. TICKLESS_KERNEL mode is now the default on all architectures.

The Symmetric Multi-Processing (SMP) subsystem continues to evolve with the addition of a new CPU affinity API that can “pin” threads to specific cores or sets of cores. The core kernel no longer uses the global irq_lock on SMP systems, and exclusively uses the spinlock API (which on uniprocessor systems reduces to the same code).
While this release marks the culmination of one of the largest and most ambitious efforts undertaken by the Zephyr Project to date, it is just the beginning. Work has already begun on a number of major initiatives including obtaining functional safety certification of the core OS. 


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