This is a 90% linear-shrink process from 65nm including I/O and analogue circuits (this is a key factor) to give significant die cost savings over 65nm with the same speed and 10 to 20% lower power consumption.
Because the 55nm process is a direct shrink, designers can use existing libraries and port their 65nm designs with minimal risk and effort. The 55nm logic family includes general purpose (GP) and consumer (GC) platforms and initial production of the 55GP begins this quarter, with Nvidia and Altera expected to be lead customers, followed later in the year by 55GC. A shuttle service with wafers from multiple customers will start in May.
“TSMC’s half-node process, including 55nm, is the quickest and simplest way for our customers to be cost competitive in the rapidly changing marketplace,” said Jason Chen, vice president of corporate development of TSMC. “TSMC continues to combine manufacturing superiority with a comprehensive design ecosystem to support customers of any size, from startups to multinational giants.”
The company has been offering half-node processes for six technology generations starting from 0.35um.
45nm test devices are already running at TSMC and at IBM for production next year.