8 RISC-V pioneer SiFive is to lay off around 130 staff, around 20% as it re-align its business in supplying IP to chip designers.
7 European chip designer Tachyum is to build a supercomputer for a US customer that will be capable of 50 exaFLOP performance using its Prodigy chip that is set to sample shortly.
6 Mathematics from the 18th century is showing a way to simpler AI models compared to today’s models with billions of parameters.
5 SemiDynamics in Spain is showing the first fully coherent RISC-V Tensor unit for AI chip design
4, 3IEDM coverage was also popular in October. Micron showed a DRAM-like non-volatile memory for AI, while Intel, TSMC both reported on stacked complementary FETs (CFETs) that are expected to be the successor to gate all around (GAA) devices for sub-1nm process. The conference also saw a compound semiconductor design from imec achieving record 1.46THz frequency for 6G applications.
2 TSMC looks to standardise chiplet protocols in a move that could shake up the development of complex chips.