Thursday, September 17, 2015

UltraSoC adds deadlock detection to its SoC analysis, debug and profiling tools

By Nick Flaherty www.flaherty.co.uk


One of the biggest challenges with developing software for embedded systems is deadlocks, where processors hang or stall as a result of complex interactions of the data. While this is traditionally tackled at the board level with a probe and logic analyser, it's a nightmare when the system is all inside a chip.

So when Cambridge-based tool developer UltraSoC adds deadlock detection capabilities into its embedded system-on-chip (SoC) analysis, profiling and debug, it's a big thing. The new analysis features allow embedded SoC architects, developers and debug engineers to detect and diagnose those hard-to-find corner cases which can cause complex SoCs to hang or stall intermittently and unpredictably, sometimes after days of continuous normal operation.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs,” said Gadge Panesar, chief technology officer of UltraSoC. “These conditions are a major contributor to the current crisis in the SoC industry. Conventional approaches either ignore the problem, or attempt to deal with it by generating massive, unmanageable data sets. UltraSoC takes a smarter approach, focusing on generating meaningful, actionable information; for the first time chip design teams can truly understand the behaviour of today’s complex SoCs.”

Bus deadlocks occur when a processor is waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives. Traditionally, the only way of isolating such problems has been to attempt to continuously trace and output all bus activity, requiring a high-bandwidth off-chip connection to gather the data, and difficult offline analysis software of huge data-sets. The UltraSoC technology uses a “smart” on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

This allows chip designers to efficiently and intelligently “look inside” their products, at wire speed, during normal operation, rather than having to pull out a trace of all the activity and go over millions of data points. The new deadlock detection capabilities are targeted at particularly difficult conditions that can cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

Software deadlocks are increasingly common in today’s SoCs. In a typical scenario, two different software processes might use a locking mechanism to govern shared access to common on-chip resources: for example another core, hardware peripherals or the capabilities of another software process. Problems can arise when each CPU believes that the other has locked its access to the shared resources. In this case UltraSoC provides an on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important. A key advantage is that UltraSoc is not tieed to any one architecture, supporting many different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others), making it possible to solve these situations.

SoC debug and silicon validation are key challenges facing the global electronics industry today. UltraSoC’s technology creates an on-chip debug infrastructure that enables pre- and post-silicon debug, reducing the risks in chip design, improving time-to-market, increasing quality and reducing costs.

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