The increased focus on 'edge' processing is driving more FPGA technology further into embedded sensor systems.
One interesting move comes from Lattice Semiconductor (currently being taken private by a private equity fund) with the iCE40 UltraPlus FPGA devices. This latest addition to the iCE40 Ultra family delivers eight times more memory (1.1 Mbit RAM), twice the digital signal processors (8x DSPs), and improved I/Os over previous generations. Available in multiple package sizes, the programmable nature of the iCE40 UltraPlus device is ideal for smartphones, wearables, drones, 360 cameras, human-machine interfaces (HMIs) and industrial automation, as well as security and surveillance products.
Lattice is also aiming the iCE40 UltraPlus at voice recognition, gesture recognition, image recognition, haptics, graphics acceleration, signal aggregation, I3C bridging and more. This brings added intelligence to smartphones and IoT edge products, such as wearables and home audio assisted devices, to be always on, always listening and ready to instantly process commands locally without going to the cloud.
This edge processing approach is concentrated around a highly energy-efficient method for computing algorithms quickly and locally using dissimilar processors to offload power hungry application processors (APs) in battery-powered devices. More DSPs offer the ability to compute higher-quality algorithms, while increased memory allows data to be buffered for longer low-power states. The flexible I/Os enable a more distributed heterogeneous processing architecture. This combination provides flexibility to enable OEMs and the Maker market to quickly deliver key innovations, such as always on sensor buffers and acoustic beam forming.
Applications include always-on sensor buffer and distributed processing for mobile devices at sub-1 mW power consumption, always-on sensor functionality while the AP is in sleep mode and supporting functions such as gesture detection, facial recognition, audio enhancement, audio beam forming, phrase detection, double tap, shake-to-wake and pedestrian dead reckoning (PDR).
The initial designs are aggregating various GPIOs, SPI, UART, I2C, I3C signals and more over a single PCB trace eliminates routing contention issues to reduce system cost and simplify the layout, but once the processing is available in the edge system there are many other opportunities.
“Distributed processing demands are increasing in mobile applications and Lattice’s iCE40 UltraPlus is optimized to address these requirements. As the newest addition to our iCE40 Ultra family, the iCE40 UltraPlus FPGAs expand its market reach to system designers who require FPGA functionality with improved DSP compute power, more I/Os and increased memory for buffering,” said C.H. Chee, senior director of marketing, mobile and consumer division at Lattice Semiconductor. “Our solution will reduce design complexity, system power consumption and time-to-market, while enhancing responsiveness of tomorrow’s mobile devices.”
The family provides 1.1 Mbits of SRAM, 8 DSP blocks, up to 5K LUTs (look up tables for programmable logic) and Non-Volatile Configuration Memory (NVCM) for instant-on applications with MIPI-I3C support for low-resolution, always-on camera applications and under 100 micro watt of standby power consumption. The QFN packages mean the FPGAs can fit into 2.15 x 2.55 mm for space-constrained consumer markets.
The iCE40 UltraPlus product evaluation samples and boards are now available at www.latticesemi.com/iCE40UltraFamily.
The initial designs are aggregating various GPIOs, SPI, UART, I2C, I3C signals and more over a single PCB trace eliminates routing contention issues to reduce system cost and simplify the layout, but once the processing is available in the edge system there are many other opportunities.
“Distributed processing demands are increasing in mobile applications and Lattice’s iCE40 UltraPlus is optimized to address these requirements. As the newest addition to our iCE40 Ultra family, the iCE40 UltraPlus FPGAs expand its market reach to system designers who require FPGA functionality with improved DSP compute power, more I/Os and increased memory for buffering,” said C.H. Chee, senior director of marketing, mobile and consumer division at Lattice Semiconductor. “Our solution will reduce design complexity, system power consumption and time-to-market, while enhancing responsiveness of tomorrow’s mobile devices.”
The family provides 1.1 Mbits of SRAM, 8 DSP blocks, up to 5K LUTs (look up tables for programmable logic) and Non-Volatile Configuration Memory (NVCM) for instant-on applications with MIPI-I3C support for low-resolution, always-on camera applications and under 100 micro watt of standby power consumption. The QFN packages mean the FPGAs can fit into 2.15 x 2.55 mm for space-constrained consumer markets.
The iCE40 UltraPlus product evaluation samples and boards are now available at www.latticesemi.com/iCE40UltraFamily.
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