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Friday, June 07, 2019

First platform certified for 5nm design at Samsung

By Nick Flaherty www.flaherty.co.uk

Samsung Electronics has certified the Synopsys Fusion Design Platform for its 5nm Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology. 

The AI-enhanced, cloud-ready Fusion Design Platform certified with the 64bit Arm Cortex-A53 and Cortex-A57 processors, which are based on the Armv8 architecture. This is a full flow for the next wave of semiconductor designs, including high-performance computing (HPC), automotive, 5G, and artificial intelligence (AI) market segments.

"Through our 7-nanometer product shipment and the successful completion of 5-nanometer process development, we've proven our capabilities in EUV-based nodes. Using the Synopsys Fusion Design Platform, our mutual customers will be able to design the most competitive 5LPE SoC products for the full entitled performance and low power applications," said JY Choi, vice president of Foundry Design Technology Team at Samsung Electronics. "Synopsys continues to be our vendor of choice for collaboration on new node development and enablement, so our foundry customers can confidently ramp their designs to volume production in all market segments, including automotive, AI, high-performance computing, and mobile."
The platform includes the Fusion Compiler RTL-to-GDSII Solution, along with IC Compiler II place-and-route with EUV single-exposure-based routing with optimized 5LPE design rule support, single fin variant-aware legalization, and via stapling to ensure maximum utilization while minimizing dynamic power

It also includes Design Compiler Graphical and Design Compiler NXT RTL synthesis for correlation, congestion reduction, pin access-aware optimization, 5LPE design rule support, and physical guidance for IC Compiler II 

The IC Validator physical signoff is a cloud-optimized physical signoff including DRC, LVS, and Fill. Innovative Explorer DRC and Live DRC technologies for enhanced productivity, while PrimeTime timing signoff provides near-threshold ultra-low voltage variation modeling, via variation modeling, and placement rule-aware engineering change order (ECO) guidance

StarRC parasitic extraction provides the EUV single pattern-based routing support, and new extraction technologies, such as coverage-based via resistance and vertical gate resistance modeling while an ANSYS RedHawk-driven EM/IR analysis and optimization within place-and-route.

For test, the TestMAX DFT and TestMAX ATPG test provide FinFET-based, cell-aware, and slack-based transition testing for higher test quality. Formality equivalence checking provides UPF-based equivalence checking with state transition verification

The platform is in active production usage at market-leading companies. The AI-enhanced platform boosts designer productivity by speeding up computation-intensive analyses and uses past learning to improve the results. It runs on major public cloud providers' and Synopsys-hosted infrastructure.

"Our long and successful collaboration with Samsung Foundry has enabled our mutual customers to adopt Synopsys' market-leading solutions early, certified on Samsung's most advanced node," said Sassine Ghazi, general manager of Synopsys' Design Group. "Combining the 5LPE benefits in power, performance, and gate density with the Synopsys Fusion Design Platform QoR and TTR advantages will enable our mutual customers to differentiate their next-generation products. Synopsys continues to focus on providing the best solutions for joint customers."

www.synopsys.com

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