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Monday, October 07, 2019

NXP ARM multicore processors get Lynx hypervisor

By Nick Flaherty www.flaherty.co.uk

NXP's QorIQ Arm-based processors can now use the LynxSecure Separation Kernel Hypervisor for to keep applications separate in avionics designs.

Lynx has ported LynxSecure onto the NXP QorIQ Layerscape 1046A (LS1046A) multicore communication processor integrating quad 64-bit Arm Cortex-A72 cores. This joins the existing support for NXP S32V234 MPSoC.
“Multicore architectures are seeing increasing adoption in avionics systems due to performance requirements and the lack of availability of single core processors," said Geoff Waters, Senior Principal Engineer at NXP Semiconductors and Chairman of the NXP- led Multicore for Avionics Working Group. "The porting of LynxSecure separation kernel hypervisor technology is an important step forward. It offers an exceptional technology for managing the complexity associated with multicores, reducing the design and certification time for safety critical systems based on NXP Layerscape SoCs.”

David Beal, Director of Product Marketing at Lynx Software Technologies, added, “Increasingly, avionics, transportation and other safety-critical systems rely on redundant platforms. Now, system architects and engineers who have strict requirements around performance, safety and security can take full advantage of the features and capabilities offered by NXP LS1046A within a straight-forward, secure-by-design software systems architecture that is enabled by LYNX MOSA.ic. The combination results in high performance and immutable security while preserving modularity and providing a natural path for future software-migration as newer, processing platforms become available.”

The LynxSecure separation kernel forms the foundation of the LYNX MOSA.ic framework to address markets such as avionics, transportation, industrial and medical systems. By providing the highest levels of performance, security and safety protections, LYNX MOSA.ic enables complex, systems that are responsible for both critical and non-critical functions. This reduces system design, integration, test and certification efforts.


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