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Wednesday, March 04, 2020

CEVA lays claim to world's most powerful DSP

By Nick Flaherty

CEVA has launched its fourth generation digital signal processor architecture that it says is the world's most powerful.

The scalar and vector processing in the XC architecture supports double 8-way VLIW and up to 14,000 bits of data level parallelism. All this supports performance of up to 1,600 GOPS, dynamic multithreading and advanced pipeline to reach operating speeds of 1.8GHz at 7nm.

The architecture, available as IP for a system-on-chip (SoC), is aimed at complex parallel processing workloads required for 5G endpoints and Radio Access Networks (RAN), enterprise access points and other multigigabit low latency applications.
The design is fully synthesizable, and the multithreading design allows the processors to be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. 

CEVA has also developed a new memory subsystem with a wide 2048-bit memory bandwidth, with coherent, tightly-coupled memory to support efficient simultaneous multithreading and memory access.

"The dynamically reconfigurable multithreading and high speed design, along with comprehensive capabilities for both control and arithmetic processing, sets the foundation for the proliferation of ASICs and ASSPs for 5G infrastructure and endpoints," said Mike Demler, Senior Analyst at The Linley Group.

The first processor based on the Gen4 CEVA-XC architecture is the multicore CEVA-XC16 for 5G RAN architectures including Open RAN (O-RAN), Baseband Unit (BBU) aggregation as well as Wi-Fi and 5G enterprise access points. The CEVA-XC16 is also applicable to massive signal processing and AI workloads associated with base station operation.

The XC16 has been specifically designed for the 3GPP release specifications in mind, building on CEVA's experience with leading wireless infrastructure vendors for their cellular infrastructure ASICs. The previous generation CEVA-XC4500 and CEVA-XC12 DSPs are used in chips in 4G and 5G cellular networks today, and the CEVA-XC16 is already in design with a leading wireless vendor for their next-generation 5G ASIC.

The XC16 can be reconfigured as two separate parallel threads running simultaneously, sharing their L1 Data memory with cache coherency, which directly improves latency and performance efficiency for PHY control processing, without the need for an additional CPU. This boosts the performance per square millimeter by 50% compared to a single-core/single-thread architecture when massive numbers of users are connected in a crowded area. This amounts to 35% die area savings for a large cluster of cores, as is typical for custom 5G base station silicon.

Other key features in the CEVA-XC16 include the latest dual CEVA-BX scalar processor units, dynamic allocation of vector units resources to processing threads and scalar control architecture and tools that reduce code size by a third through dynamic branch prediction and loop optimizations alongside an LLVM based compiler.

The XC16 introduces a new instruction set architectures for FFT and FIR operations common in wireless systems that doubles performance, with a simple software migration path from previous generations CEVA-XC4500 and CEVA-XC12 DSPs.

"5G is a technology with multiple growth vectors spanning consumer, industrial, telecom and AI. Addressing these fragmented and complex use cases requires new thinking and practices for processors," said Aviv Malinovitch, Vice President and General Manager of the Mobile Broadband Business Unit at CEVA. "Our Gen 4 CEVA-XC architecture encapsulates this new approach, enabling never-before-seen DSP core performance through groundbreaking innovations and design. The CEVA-XC16 DSP is evidence of this and serves to substantially reduce the entry barriers for OEMs and semiconductor vendors looking to benefit from the growing 5G Capex and Open RAN network architectures."

The CEVA-XC16 is available for general licensing starting in Q2 2020. 

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