Researchers at HP Labs have developed a technique that they think could eventually dramatically increase the density of programmable gate array devices (or reduce the size and power).
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS (complementary metal oxide silicon), using an architecture HP Labs researchers have named “field programmable nanowire interconnect (FPNI)” – a variation on the well-established FPGA technology.
The research, by Greg Snider and Stan Williams of HP Labs, is a featured paper in the Jan. 24 issue of Nanotechnology (published here in Bristol, where HP also has it's European Lab) The research was conducted using classic modeling and simulation techniques, but Williams said HP is working on producing an actual chip using the approach, and could have a laboratory prototype completed later this year.
“As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics,” said Williams, an HP Senior Fellow and director of Quantum Science Research at HP Labs. “Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
The work uses a conceptual breakthrough for connecting a crossbar to CMOS by Dmitri Strukov and Konstantin Likharev of Stony Brook University in New York. The HP approach relies on extensive experience in fabricating crossbars and makes a number of changes designed to improve the manufacturability of the circuits.
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.
The researchers presented a “conservative” chip model using 15-nanometer-wide crossbar wires combined with 45-nm half-pitch CMOS, which they said they believe could be technologically viable by 2010. That would be equivalent to leaping ahead three generations on the International Technology Roadmap for Silicon without having to shrink the transistors, they said.
Then there are flights of the future, with a model based on 4.5-nm-wide crossbar wires, which they said could be ready by 2020. The 4.5-nm crossbar architecture combined with 45-nm CMOS would yield a hybrid FPGA about 4 percent the size of a 45-nm CMOS-only FPGA (or ten times the density, until limited by the transistor power). The size and power savings at this level will be a tradeoff that will be determined in ten or more years, so it's a very long way away.
One of the challenges will be yield, as the small size of the cross bar on the upper layers will make it sensitive to defects, adn that will also hit the cost, so don't write off traditional CMOS and Xilinx and Altera just yet.