Arizona State stacks nanoscale memory chips

Researchers improve chip memory by stacking cells

Researchers at Arizona State University have developed an elegant method for significantly improving the memory capacity of electronic chips.
The researchers have shown that they can build stackable memory based on 'ionic memory technology' which could make them ideal candidates for storage cells in high-density memory. Best of all, the new method uses well-known electronics materials.
“This opens the door to inexpensive, high-density data storage by ‘stacking’ memory layers on top one another inside a single chip,” said Michael Kozicki, an ASU electrical engineering professor and director of the Center for Applied Nanoionics. “This could lead to hard drive data storage capacity on a chip, which enables portable systems that are smaller, more rugged and able to go longer between battery charges.”
“This is a significant improvement on the technology we developed two years ago where we made a new type of memory that could replace Flash, using materials common to the semiconductor industry (copper-doped silicon dioxide). What we have done now is add some critical functionality to the memory cell merely by involving another common materia – silicon.”
Kozicki outlined the new memory device in a technical presentation he made in November at the 2009 International Electron Devices and Materials Symposia in Taiwan. Kozicki said that given current technology, electronics researchers are fast reaching the physical limits of device memory. This fact has spurred research into new types of memory that can store more information into less and less physical space. One way of doing this is to stack memory cells.
Kozicki said stacking memory cells has not been achieved before because the cells could not be isolated. Each memory cell has a storage element and an access device; the latter allowing you to read, write or erase each storage cell individually.
“Before, if you joined several memory cells together you wouldn’t be able to access one without accessing all of the others because they were all wired together,” Kozicki said. “What we did was put in an access, or isolation device, that electrically splits all of them into individual cells.”
Up until now, people built these access elements into the silicon substrate.
“But if you do that for one layer of memory and then you build another layer, where will you put the access device,” Kozicki asked. “You already used up the silicon on the first layer and it’s a single crystal, it is very difficult to have multiple layers of single crystal material.”
The new approach does use silicon, but not single crystal silicon, which can be deposited in layers as part of the three-dimensional memory fabrication process. Kozicki said his team was wrestling with how to find a way to build a diode into the memory cell. The diode would isolate the cells.
Kozicki said this idea usually involves several additional layers and processing steps when making the circuit, but his team found an elegant way of achieving diode capability by substituting one known material for another, in this case replacing a layer of metal with doped silicon.
“We can actually use a number of different types of silicon that can be layered,” he said. “We get away from using the substrate altogether for controlling the memory cells and put these access devices in the layers of memory above the silicon substrate.”
“Rather than having one transistor in the substrate controlling each memory cell, we have a memory cell with a built-in diode (access device) and since it is built into the cell, it will allow us to put in as many layers as we can squeeze in there,” Kozicki said. “We’ve shown that by replacing the bottom electrode with silicon it is feasible to go any number of layers above it.
With each layer applied, memory capacity significantly expands.
“Stackable memory is thought to be the only way of reaching the densities necessary for the type of solid state memory that can compete with hard drives on cost as well as information storage capacity,” Kozicki said. “If you had eight layers of memory in a single chip, this would give you almost eight times the density without increasing the area.”

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