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Monday, September 26, 2011

Xelerated starts shipping 100G network processor

HX 100G NPU offers programmable wirespeed processing, advanced traffic management and low power consumption
By Nick Flaherty

Swedish chip designer Xelerated has started volume production of its HX family of 100G network processors (NPU) for packet-OTN, mobile backhaul/PTN and Carrier Ethernet Switch-Routers. 
The HX family of NPUs was the first to demonstrate 100G wirespeed network processing last year and has now been designed into 20 systems with the first going into production later this year. Compared to legacy NPUs, the HX family typically reduces power consumption per processed gigabit of traffic by 67 percent.
“The high demand for the HX family of NPUs is due to its combination of low power consumption, programmable wirespeed processing and integration of advanced traffic management,” said Anders Ericsson, VP of Sales and Marketing at Xcelerated. “These platforms have the potential to reshape the Carrier Ethernet market.”
System vendors are constantly challenged to add new services and features to their Ethernet and IP/MPLS data planes. To increase feature velocity, data planes are increasingly implemented using network processors, which are flexible and can be enhanced through software upgrades. Designed for pizza box and line card slot capacities of 20-200 Gbps, the HX family integrates inherent wirespeed processing and advanced traffic management with deep packet buffering.
In packet-OTN systems, the HX NPU enables Ethernet/MPLS services for 100 Gbps of traffic using a single chip. These line cards are designed for aggregation and transport, and support a range of interface types including GE, 10GE, 40GE, 100GE and OTU0-OTU4. In mobile backhaul, the HX family implements complete L2 and L3 switch-router applications.
“System vendors are increasingly faced with power budget restrictions as they scale to accommodate new services and greater port densities,” said Bob Wheeler, senior analyst at The Linley Group. “Xelerated's 100G NPU is hitting a sweet spot in designs where programmability is required but footprint and power budget are scarce.”
The HX family of NPUs provides a unique line-card-on-a-chip approach, including:
  • Dataflow architecture featuring industry-leading 448 PISC processor cores and 28 engine access points to connect to on-chip or off-chip table memory and hardware engines
  • Advanced traffic manager with hierarchical per-user, per-service scheduling and shaping and deep off-chip packet buffer fully implemented in cost-effective DDR3 DRAM
  • Embedded switching with advanced pre-classification for intelligent oversubscription
  • Internet-scale forwarding of IPv4 and IPv6 through high-performance memory interfaces to off-chip TCAM, SRAM and DDR3 DRAM
  • Synchronous Ethernet and support for one-step PTP IEEE-1588
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