Wednesday, May 25, 2016

Cortus brings fast crypto to home IoT designs

Microprocessor core developer Cortus has teamed up with Oberon Microsystems in Switzerland to to implement fast encryption technology to secure the Internet of Things in the home.

The highly efficient cryptographic code, a key component of its OberonHAP product, has been ported to a 50MHz Cortus APS3RP 32-bit IP core. The combination of the tiny software memory footprint and minimalist processor core is well suited to secure ASICs in battery-powered home automation devices.

Oberon Microsystems has developed, analysed and optimised the cryptographic code of OberonHAP since 2013 (see below). They have developed – and formally proved - novel algorithm combinations, and have carefully written critical parts in assembly language for high performance. The resulting software is typically three times as fast as a good implementation in C. OberonHAP thus makes secure home automation feasible even on low-power, low-cost 32-bit microcontroller cores for ASICs.



Home automation is a key application area for Cortus”, says Michael Chapman, CEO and President of Cortus, “So we are delighted to see the first steps completed in making Oberon’s code available for Cortus licensees. With growing connectivity of home devices, security is essential." 

OberonHAP implements a range of cryptographic algorithms for pairing, authentication and encryption such as:

For an integrated circuit with the processor core running at 50 MHz, the cryptographic processing of the SRP algorithm – which is required once in the lifetime of a home automation device – takes less than five seconds. Cryptographic processing during opening of a session between a device and a smartphone takes less than 100 milliseconds. RAM requirements were brought down to a record-low 2.5 KB.

“The combination of Oberon’s optimised cryptographic code and the APS3RP results in very good performance even on low-cost, low power devices”, said Cuno Pfister, managing director of Oberon microsystems AG, “We look forward to further cooperation with Cortus in the area of security for home appliances.”

The APS3RP is an enhanced performance version of the widely-deployed APS3R and provides a single cycle parallel multiplier. It has a Harvard architecture and a 3-stage pipeline. The Cortus family of APS processors offers a wide choice of computational performance and system complexity for embedded SoCs. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.

The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII, Micrium μC/OSIII and Blunk TargetOS. To date over 900 million devices have been manufactured containing Cortus processor cores.
By Nick Flaherty www.flaherty.co.uk

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