Tuesday, August 08, 2017

First debug and analytics for ARM’s AMBA 5 CHI tackles 'fierce' challenge

By Nick Flaherty www.flaherty.co.uk

UltraSoC has developed IP for full debug and monitoring of ARM’s recently announced AMBA 5 Coherent Hub Interface (CHI) Issue B, a 'fiercely challenging' problem.

UltraSoC is the only monitoring and debug product supporting CHI Issue B, which is ARM’s most advanced bus specification for complex system-on-chip (SoC) designs.

Delivered as semiconductor IP, this enables reliable testing and problem solving of next-generation cache-coherent SoC designs based on the CHI Issue B specification, enabling customers to benefit from CHI Issue B’s enhancements to security, data throughput and latency. 

“CHI is an increasingly significant protocol in delivering critical performance for on-chip networked SoCs: but it’s a fiercely challenging standard to design with, particularly after the update to Issue B,” said Gadge Panesar, UltraSoC CTO. “Simple performance statistics are useful, but far from sufficient, and that’s where a solution – and a team – like UltraSoC’s, focused on monitoring and debug, can really help. It’s a great strength of the ARM ecosystem that customers can call on third-party solution-providers like UltraSoC, who have the expertise to help designers quickly and simply get up to speed with issues like coherent design.”

The support for CHI Issue B continues UltraSoC’s approach of offering more system-level monitoring and debug than ARM’s CoreSight. Designers can use UltraSoC as an ‘overlay’ to access features not provided in their traditional debug system; or can opt to completely replace those systems with UltraSoC. This approach to debug is particularly useful in multi-core designs: UltraSoC provides support for all common proprietary CPU architectures, as well as open-source processor platforms such as RISC-V.

Modern SoCs, particularly those used in highly-complex data centre, enterprise IT, or automotive applications, rely on interconnections with the hub of a network-on-chip (NoC). The AMBA 5 CHI specification was developed to ensure that the interconnect itself does not become a bottleneck when traffic and system complexity rise. Designers can choose how to implement CHI according to the required balance of power, performance and area. However, in these SoC design and system choices there are potential issues which may impact system performance, such as traffic issues related to cache coherency. By using UltraSoC’s monitor IP for CHI Issue B, designers of these complex SoCs can quickly check performance, diagnose and predict such issues.

The CHI Issue B specification incorporates a series of significant updates that directly address latency and throughput enhancements. Two of the most significant enhancements are far atomic operations and cache stashing. Far atomic operations enable the interconnect to perform high frequency updates to shared data. Cache stashing allows accelerators or IO devices to stash critical data within a CPU cache for low latency access.

UltraSoC launched the industry’s first monitoring and debug IP for the earlier (version A) AMBA 5 CHI NoC specification last year, extending its family of protocol-aware monitors for on-chip interconnect, and allowing both debugging and fine-tuning of the NoC fabric. 

Since then, the company has worked closely with lead customers in developing a CHI Issue B solution that can be used to verify custom implementations of the protocol; to facilitate integration with the overall chip design; and to tune the NoC so that bus overhead is minimized.



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