Renesas Electronics has launched its third-generation 32bit RX CPU core, the RXv3.
The five stage superscalar CISC core will be used in the RX600 and RX700 families (see below) that will begin rolling out at the end of 2018, aimed at the real-time performance and enhanced stability required by motor control and industrial applications in next-generation smart factory, smart home and smart infrastructure equipment.
The RX core consolidated features from the Hitachi SH, Mitsubishi M16C and previous Renesas devices, and the RXv3 core boosts the five stage superscalar core architecture with up to 5.8 CoreMark/MHz, up from a peak of 4.55 in RXv2. It also adds options for register bank save functions and an optional double precision floating point capability but will be binary compatible with the RXv2 and RXv1 CPU cores to preserve the code base. Using a CISC core tends to give better code density.
“The cutting-edge RXv3 core technology targets a wide range of embedded applications in the industrial IoT era where ever increasing system complexity places higher demands on performance and power efficiency,” said Daryl Khoo, Vice President Product Marketing, IoT Platform Business Division at Renesas.
The RXv3 core will enable the first RX600 MCUs to achieve 44.8 CoreMark/mA with an energy-saving cache design that reduces both access time and power consumption during on-chip flash memory reads, such as instruction fetch.
The RXv3 core achieves significantly faster interrupt response times with a new option for single-cycle register saves. Using dedicated instruction and a save register bank with up to 256 banks, designers can minimise the interrupt handling overhead required for embedded systems operating in real-time applications such as motor control. This means the RTOS context switch time is up to 20 percent faster.
Using model-based development (MBD) has enabled the DP-FPU to help reduce the effort of porting high precision control models to the MCU. Similar to the RXv2 core, the RXv3 core performs DSP/FPU operations and memory accesses simultaneously to substantially boost signal processing capabilities.