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Monday, October 29, 2018

Cypress integrates Pelion IoT platform into PSoC6

By Nick Flaherty www.flaherty.co.uk

Cypress Semiconductor has expanded its collaboration with Arm to integrates the Arm Pelion IoT Platform with Cypress’ ultra-low power, dual-core PSoC 6 microcontrollers (MCUs) and CYW4343W Wi-Fi and Bluetooth combo radios for robust wireless connectivity. PSoC 6 provides Arm v7-M hardware-based security that adheres to the highest level of device protection defined by the Arm Platform Security Architecture (PSA).

Cypress and Arm are demonstrating hardware-secured onboarding and communication through the integration of the dual-core PSoC 6 MCU and Pelion IoT Platform. The PSoC 6 MCU is running Arm’s PSA-defined Secure Partition Manager to be supported in Arm Mbed OS version 5.11 open-source embedded operating system, which will be available this December. Developers can leverage the private key storage and hardware-accelerated cryptography in the PSoC 6 MCU for cryptographically-secured lifecycle management functions, such as over-the-air firmware updates, mutual authentication, and device attestation and revocation.

“Secure device management is critical for the IoT to scale, and OEMs require solutions that help them to easily manage devices throughout their lifecycles,” said Hima Mukkamala, senior vice president and general manager, IoT Cloud Services at Arm. “By partnering with companies such as Cypress, we are enabling a more secure environment from device-to-data.”

“Cypress is making a strategic push to integrate security into our compute, connect and store portfolio for the IoT,” said Sudhir Gopalswamy, Executive Vice President of Cypress’ Microcontrollers and Connectivity Division. “Our continued collaboration with Arm is focused on delivering secure, easy-to-use solutions and is an important part of our strategy to enable IoT designers to quickly develop, deploy and manage secure IoT edge nodes.”

The PSoC 6 architecture is built on ultra-low-power 40nm process technology, and the MCUs feature low-power design techniques to extend battery life up to a full week for wearables. The dual-core Arm Cortex-M4 and Cortex-M0+ architecture lets designers optimise for power and performance simultaneously. Using its dual cores combined with configurable memory and peripheral protection units, the PSoC 6 MCU delivers the highest level of protection defined by the Platform Security Architecture (PSA) from Arm. 

Designers can use the MCU’s software-defined peripherals to create custom analogue front-ends (AFEs) or digital interfaces for system components such as electronic-ink displays. The PSoC 6 links to the CapSense capacitive-sensing technology, enabling modern touch and gesture-based interfaces that are robust and reliable. 


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