MRAM opens up low power IoT applications

By Nick Flaherty www.flaherty.co.uk

After years of development, magnetoresistive RAM (MRAM) looks set to become a standard technology as it rolls out on the 22nm process technology from GLOBALFOUNDRIES. The move will allow lower power IoT chip designs coming to market in 2018.

GLOBALFOUNDRIES had been working with startup Everspin Technologies, and has now introduced a scalable, embedded MRAM non-volatile memory technology (eMRAM) on its 22FDX platform.

This provides embedded system designers with access to 1,000x faster write speeds and 1,000x more endurance than today’s non-volatile memory (NVM) offerings. 22FDX eMRAM also features the ability to retain data through 260°C solder reflow with an industry-leading eMRAM bitcell size.

The 22FDX platform is the industry’s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology which enables the MRAM capability for both code storage (flash) and working memory (SRAM).  The power efficiency of FDX and eMRAM, coupled with the available RF connectivity IP, makes 22FDX an ideal platform for battery-powered IoT products and automotive controllers.

“Customers are looking for a high-performance non-volatile memory solution that expands their product capabilities," said Gregg Bartlett, senior vice president CMOS Platforms Business Unit, GLOBALFOUNDRIES. "Our introduction of 22FDX eMRAM enables system designers with new capabilities, allowing them to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.”

“Emerging non-volatile memories are moving from the lab to the fab,” said Thomas Coughlin, President of Coughlin Associates. “GLOBALFOUNDRIES' 22FDX eMRAM will offer a major advancement in SoC capabilities, by leveraging the key performance attributes of embedded MRAM. Designers of battery powered IoT devices, automotive MCUs and SoCs and SSD storage controllers will certainly want to take advantage of this versatile embedded NVM technology.”

The partnership with Everspin has already delivered the world’s highest density ST-MRAM in August, 2016 with a 256Mbit DDR3 perpendicular magnetic tunnel junction (pMTJ) memory chip that is being readied for mass production.

The 22FDX eMRAM is currently in development and is expected to be available for customer prototyping in 2017, with volume production in 2018. GLOBALFOUNDRIES’ eMRAM technology is scalable beyond 22nm and is expected to be available on both FinFET and future FDX platforms.

www.globalfoundries.com

New process boosts ESD protection

By Nick Flaherty www.flaherty.co.uk

Electrostatic discharge (ESD) can be a major problem for embedded equipment. Static generated from everyday movement can damage silicon devices, especially as process technology means feaatures in the chips are ever smaller and more vulnerable to such electric shocks

Toshiba is hoping a new process technology it has developed to increase resistance to Electrostatic Discharge (ESD) in devices will help.

The 0.13μm process technology at New process boosts ESD protection | EETE Power Management optimizes the structure of transistor and significantly improves ESD characteristics by a factor of four, while the standard deviation is only 1/12 that of the conventional structure. Analysis of 3D simulations has also allowed Toshiba to identify a mechanism for optimizing transistor structure to boost ESD robustness.

ESD protection devices are required to protect internal circuit and this is particularly true for analogue power semiconductor devices required to apply 10V to 100V, which need a high rated voltage. In this case, ESD protection devices must ensure high current flow, which results in enlarged chip size. Shrinking the size of the ESD protection device is an issue in realizing more compact chips.

Using 3D simulation analysis of an ESD event, Toshiba found out that ESD induced destruction is caused by lattice temperature increase due to the current flowing at the highest electric field point. Modifying the transistor structure, which extending the drain low resistive region to the source direction and suppressing the lateral silicon resistance, shifts the current flow from the bottom of the drain to source direction and detaches it from the highest electrical field point. This optimized design was found to increase ESD robustness by up to four times and to decrease the standard deviation down to 1/12. In addition, the device size required to ensure a HBM (Human Body Model) of ±2000V was cut by 68%.

Toshiba offers advanced analog process platforms, with 0.13μm process technology, that can be embedded with the transistors such as CMOS, DMOS, bipolar transistor and the passive devices such as resistor and capacitor. User can select a process suited to each application from three process platforms: “BiCD-0.13” is mainly for automotive (DMOS line up is up to 100V); “CD-0.13BL” is mainly for motor control drivers