But the deal is much more about interconnect – the Torrenza initiative announced in June is about connecting up the AMD processors to other processors and to co-processors, such as FPGAs, via the Hypertransport interconnect. The new generation of FPGAs from Xilinx (Virtex 5 LXT) and Altera (expect a Stratix 3 GX) will have high speed, multi-gigabit interfaces on them that will help this along.
AMD also announced, in conjunction with the Computer Architecture Group at the University of Mannheim in Germany, the creation of the Mannheim Center of Excellence (COE), for research for HyperTransport technology. As the only current academic licensee of coherent HyperTransport (cHT), the research at the Mannheim COE is expected to directly benefit the academic community and the development of next-generation technology that leverages HyperTransport. Early results from the Mannheim COE research include the release of an HTX board for universities and companies that research compute-intensive testing and design applications.
“These activities in support of Torrenza represent fresh thinking in the application of open standards in creating collaborative research environments that can directly benefit customers,” said Michael Goddard, director of Performance Computing at AMD. “Academic customers are already seeing the results of the HyperTransport expertise the Mannheim COE can deliver, while OpenFPGA is leveraging best practices to provide a programming model for FPGAs, one of the co-processing technologies embraced by Torrenza. Ultimately, these efforts will further the adoption of HyperTransport technology and computing based on Direct Connect Architecture, offering new levels of stability and upgradeability in open environments such as AMD64.”