It may seem like a strange joke for an engineer - When is an instruction set architecture not an instruction set architecture? Well, according to ARM, when it’s a ‘lightweight profile’.
ARM has developed a core, the Cortex M1, specifically targeted at the FPGA market, but is mucking around with the ISA - something that is usually sacrosanct
By using a three stage von Neuman architecture in the core, the Cortex M1 core takes up less space than the previous ARM7 core already available on Actel FPGAs.
This will also be aimed at large OEM equipment makers to take ARM licenses directly, rather than through an ASIC company or chip design.
The new core will be compatible with M3 cores used in low cost microcontrollers and high volume ASICs. It uses "a lightweight profile of the Thumb 2 instruction set," said Dominic Pajak, product manager for the processor division at ARM. This means that existing 32bit ARM code will not run on it, and 16bit Thumb 1 code will need additional 32bit instructions. New Thumb 2 code will run with no problems, and real time operating systems such as uClinux, Nucleus and ThreadX will also run on the core. So for new designs, that's fine, and obviously where ARM is aiming this, but existing code will have to be recompiled for the core.
This is important as there is lots of ARM code on ARM7 microcontrollers and in existing telecoms chips using ARM7 cores that could move to the new low cost FPGA families such as Altera's Cyclone 3 - see below.
The three stage von Neuman architecture, rather than a five stage Harvard architecture like other cores in the ARM family, reduces the size of the core dramatically to less than an 8051 or ARM7 core says Pajak. But this also means it runs at a relatively slow 72MHz, although this compares to just 25MHz for the ARM7 in an FPGA.
It is currently available on Actel's Fusion and proAsic families, taking up 20% of a 1m gate part or a third of a 600,000 gate Fusion part that includes analogue elements such as analogue to digital converters. A version for the low power Igloo family is expected at the end of the year.
The core is already part of the Actel design flow, supplied as a configurable black box that is tied to a particular part via a unique identification number and the core is included in the price of the chip without having to have a licence with ARM.
"The money comes out of the license we pay to ARM," said Vaughn Williams, managing director for Actel in Europe.
The core will be available on Xilinx and Altera parts, but only through direct deals between ARM and large OEM equipment companies. "For Xilinx and Altera users, ARM will license the RTL to selected OEMs, and currently we would license to the OEMs directly," said Pajak.
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