Santa Clara startup Tabula has introduced a groundbreaking programmable logic architecture that uses time as a third dimension to deliver unmatched capability and affordability. Tabula achieves this breakthrough by combining the Spacetime hardware that dynamically reconfigures logic, memory, and interconnect at multi-GHz rates with the Spacetime compiler that manages this ultra-rapid reconfiguration transparently. Tabula will use Spacetime to deliver 3-D devices that have significant density advantages and dramatically shorter interconnects when compared to FPGAs that use 2-D architectures. In addition, Tabula will deliver these benefits while preserving a traditional design methodology. As a result, Spacetime will enable a new class of programmable devices that combines the capability of an ASIC with the ease of use of an FPGA at price points suitable for volume production.
“The key to Spacetime and its many advantages is resolving the interconnect problem intrinsic to FPGAs,” said Steve Teig, Tabula’s President and CTO. “Almost 90% of the core area of FPGAs is devoted to the implementation and control of interconnect. Besides driving up die size and product cost, the long connections also limit performance and make timing closure more difficult. If you’re going to achieve a breakthrough in programmable capability and affordability, you have to make the interconnect more efficient, and that’s what Spacetime does.”
Tabula was founded by EDA pioneer Steve Teig and is led by Dennis Segers, former CEO of Matrix Semiconductor and former Senior Vice President and member of the board of directors at Xilinx. With support from premier venture capitalists including Greylock Partners, Benchmark Capital, New Enterprise Associates, Crosslink Capital, Balderton Capital, DAG Ventures, and Integral Capital, Tabula has over 80 patents granted around the Spacetime architecture with over 70 more pending. Tabula is developing a family of general-purpose 3PLD devices that are based on the Spacetime architecture. Tabula will initially target the programmable logic market but will also extend the benefits of programmability into markets that FPGAs cannot serve cost-effectively.
“The programmable logic market is one of the most profitable segments of the semiconductor industry,” said Dennis Segers, CEO of Tabula. “It was once one of the fastest growing as well, driven by rapid advancements in FPGA capability alongside Moore’s Law. Since 2000, however, there has been only incremental improvement in FPGA architectures and circuits from the market leaders, leaving programmable logic customers underserved and limiting growth for the industry segment. With the Spacetime architecture, Tabula will bring unprecedented value into the programmable logic space, restoring innovation into this formerly vibrant market and accelerating its growth.”
Spacetime Architecture Overview
A Spacetime device reconfigures on the fly at multi-GHz rates, executing each portion of a design in an automatically defined sequence of steps. Although manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension, resulting in a 3-D device with multiple layers or folds in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3-D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an inherently 2-D FPGA. A designer can realize all of the benefits of 3-D within a familiar methodology using the Spacetime compiler that automatically maps standard RTL into Spacetime.