Access the latest quantum technology

Quantum technology in Bristol and bath - find out more about how you can access the commercialisation of quantum technology for sensing and security

Monday, June 21, 2010

Xilinx tackles FPGA power with 28nm Series-7

Scalable from low to high density with 28nm Virtex-7, Kintex-7, and Artix-7 families

By Nick Flaherty www.flaherty.co.uk

Xilinx is tackling two of the key barriers to using FPGAs - power and cost. It is reducing the power consumption of its new 7 Series devices families by 50% over the previous generation and has developed an architecture that wil scale across three families, helping to reduce costs. However, the idea of heading into mobile equipment with some of these parts is somewhat optimisitic - low power serves more purpose in increasing channel density in networking and telecoms applications.
“The 7 series represents a new juncture for Xilinx, and the FPGA industry in general, as we bring our technology portfolio to new markets by putting a significant emphasis on lowering power consumption,” said Xilinx President and CEO Moshe Gavrielov. “In addition to delivering what we and our customers expect from Moore’s Law in terms of capacity and performance with each new generation, we continue our focus on opening programmable logic to a broader audience by delivering design platforms targeted toward the specific needs of new users and markets.”The low static power comes from a HKMG (high-K metal gate) process optimized for low static power consumption (see “Xilinx Picks 28nm High-Performance, Low-Power Process to Accelerate Platforms for Driving the Programmable Imperative”) that lowers static power consumption by 50 percent compared to the alternative 28nm high-performance process. Xilinx then applied architectural enhancements to lower dynamic power consumption both for logic and I/O, while also introducing intelligent clock-gating technology with the release of ISE Design Suite 12. The result is an FPGA series that provides 50 percent lower total power consumption compared to Virtex-6 and Spartan-6 FPGAs and 30 percent lower than alternative 28nm FPGA device families.
Designers can take full advantage of up to 4.7TMACS in DSP performance symmetric mode (2.37TMACs in non-symmetric mode) and 2 million logic cells at clock speeds of up to 600MHz, and achieve up to 2.4Tbps high-speed connectivity all while staying within their power budgets.
All 7 series FPGAs share a unified architecture that enables customers to easily scale their designs up or down in capability to reduce cost and power or increase performance and capability, thereby reducing their investment in developing and deploying products across low-cost and high-performance families. The architecture is derived from the widely successful Virtex-series-based architecture and has been designed to simplify reuse of current Virtex-6 and Spartan-6 FPGA designs. It is also supported by the EasyPath FPGA cost reduction solution for the move to fixed silicon that further improves productivity by enabling a guaranteed 35 percent cost reduction with no incremental conversion or engineering investment.
Customers who need the lower power or increased system performance and capacity provided in the new 7 series FPGAs can begin designs in Virtex-6 and Spartan-6 FPGAs and move the designs when the time is right through the adoption of the AMBA AXI interconnect standard enabling plug-and-play IP usage to help customers improve productivity and development costs.
“Integrating 6-LUT architecture and working with ARM on the AMBA specification for these devices supports IP reuse, portability, and predictability,” said Andy Norton, CTO for Systems Architecture, Cloudshield Technologies, an SAIC company. “A unified architecture, new paradigm-changing processor-centric devices and hierarchical-based design flows in next-gen tools, will result in increased productivity, flexibility, system-on-chip capabilities and portability from previous generation architectures.”
The devices use the same logic architecture, Block RAM, clocking technology, DSP slices, and SelectIO™ technology and build on previous generations of devices delivered by Xilinx’s patented Virtex series ASMBL block architecture. This next generation ASMBL architecture provides unprecedented flexibility and scalability that enables customers to most effectively use the full range of logic densities.

Xilinx 7 Series FPGA Families:
Virtex-7 Family: 2X system performance improvement at 50 percent lower power compared to Virtex-6 devices, the ultra high-end Virtex-7 family sets new industry benchmarks with 1.8X greater signal processing performance, 1.6x greater I/O bandwidth, 2X greater memory bandwidth with 2133 Mbps memory interfacing performance, and delivers the industry’s largest density FPGA with 2 million logic cells, which is 2.5X greater density than any previous or existing FPGA. EasyPath-7 devices are also available for all Virtex-7 FPGAs for a guaranteed 35% cost reduction without requiring any design conversion. Virtex-7 devices enable 400G bridging and switch fabric wired communication systems that are at the heart of the global wired infrastructure, advance RADAR systems, and high-performance computer systems that require single-chip TeraMACC signal processing capabilities, as well as the logic density, performance, and I/O bandwidth required for next generation test and measurement equipment. The Virtex-7 family will include “XT” extended capability devices with as many as 80 transceivers supporting individual line rates up to 13.1Gbps and devices that provide up to 1.9Tbps serial bandwidth. Also, these devices offer up to 850 SelectIO pins enabling the industry’s greatest number of parallel banks of 72-bit DDR3 memory interfaces supporting 2133Mbps. Future devices will also feature 28Gbps transceivers.

Kintex-7 Family: Establishing a new category of FPGAs, the Kintex-7 family delivers Virtex-6 family performance at less than half the price for a 2x price/performance improvement while consuming 50 percent less power. The family includes high-performance 10.3Gbps or lower-cost optimized 6.5Gbps serial connectivity, memory, and logic performance required for applications such as high volume 10G optical wired communication equipment. It also provides a balance of signal processing performance, power consumption, and cost to support the deployment of Long Term Evolution (LTE) wireless networks, meet the aggressive power and cost requirements required for next generation high definition 3D flat panel displays, and deliver the performance and bandwidth needed for next generation broadcast video-on-demand systems.

Artix-7 Family: Delivering 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family, the Artix-7 family uses small form-factor packaging and the unified Virtex-series based architecture to deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs. This new family meets low power performance requirements of battery-powered portable ultrasound equipment, and addresses small form factor, low power requirements for commercial digital camera lens control, as well as the strict size, weight, power, and cost (SWAPc) requirements for military avionics and communications equipment.

Availability

Early access ISE Design Suite software supporting 7 series FPGAs is now available. Initial devices will be available in Q1 of next year.

Enhanced by Zemanta

No comments: