Next generation RapidIO targets 10Gbit/s for scalable infrastructure

By Nick Flaherty www.flaherty.co.uk

RapidIO.org has launched the next generation of its interconnect architecture, targeting 25xN 100Gbit/s performance for 5G wireless and data centre infrastructure as well as industrial embedded systems.

With more than 200 million RapidIO fabric ports deployed worldwide at speeds of 6xN and 10xN 10-50 Gbit.s in analytics, wireless infrastructure, industrial and military applications, the 25xN 100 Gbit/s specification provides an open standard interconnect fabric for systems requiring heterogeneous coherent computing infrastructure that can scale with non-volatile storage.

“With the public release of the specification, our focus within our RapidIO.org Technical Working Group now shifts toward our Coherent Scale Out Task Group and our Non-Volatile Storage Task Group,” said Rick O’Connor, Executive Director of RapidIO.org. “Work on the Coherent Scale Out and Non-Volatile Storage draft specifications is progressing and we invite members of industry to join us and participate in defining these key building blocks for flexible, heterogeneous, coherent scale out of performance critical, low-latency applications over RapidIO fabrics.”

“The public release of the 25xN 100 Gbps RapidIO Specification is the culmination of efforts and contributions of RapidIO.org member companies,” said Paul Carson, Chairman of RapidIO.org and Director of IP Development at Texas Instruments. “This work extends the performance roadmap of RapidIO fabrics for use in heterogeneous systems for many years to come.”

The emergence of heterogeneous systems and next-generation non-volatile storage technologies beyond NAND Flash such as Resistive RAM (ReRAM) means fabric clusters will be key to driving scalable performance, says Dr. Zvonimir Z. Bandić,

Director of Next Generation Platform Technologies at drive maker Western Digital. “We see the public release of the 25xN 100 Gbps RapidIO Specification as a key enabling building block for these coherent, non-volatile storage based systems,” he said.

The technology will be integrated into embedded system-on-chip devices with cores from ARM and MIPS as a way to link different types of computing resources together with low latency using standalone switches from suppliers such as IDT.

“Open standard interconnects are key to ongoing energy efficiency and performance improvements across the entire SoC,” said Phil Bourekas, director of segment marketing, ARM. “The public availability of the 25xN 100 Gbps RapidIO Specification addresses ARM ecosystem developer requirements for coherent network infrastructure SoCs based on the ARMv8-A architecture, providing an available standard for systems at 5G and beyond.”

“IDT has a strategic commitment to RapidIO that spans over a decade and the public release of the 25xN 100 Gbps RapidIO Specification is a key enabling platform for wireless, HPC, cloud and industrial systems our customers are building”, said Ron Jew, General Manager, Wireless Infrastructure Products at IDT. “Through key R&D collaborations with global technology experts, such as CERN openlab, we’re able to ensure that our heterogeneous coherent scale out and storage over 100 Gbps RapidIO fabrics delivers the performance our customers in 5G infrastructure and advanced data analytics are looking for.”

“Heterogeneous computing is becoming increasingly prevalent for our customers’ next generation systems and our MIPS processor technology plays a key role in these systems,” said Jim Nicholas, EVP MIPS Processor IP at Imagination Technologies. “The release of the industry open standard 25xN 100 Gbps RapidIO Specification is a welcome addition to our ecosystem and we’ll look forward to future developments from the Coherent Scale Out Task Group.”

www.rapidio.org