Cadence and Mentor square off in design of custom IoT chips

By Nick Flaherty www.flaherty.co.uk

The growth of the Internet of Things and the large volumes for chips is creating new interest in developing custom chips for embedded applications, and two of the largest tool providers are going head to head with a low cost design flow.

While ARM is offering its M0 processor core free to evaluate (and a lower cost $40,000 commercial license), the challenge is developing a mixed signal analogue and digital chip. While Cadence Design Systems has traditionally dominated the analogue portion of the chip design flow, Mentor Graphics recently bought the analogue and MEMS design tools of Tanner, providing a competing flow.   

The custom chips can be produced at relatively low cost as part of a 180nm multi-project wafer from a supplier such as Europractice which can provide 45 samples of a 25mm2 chip for $16,000. With a relatively small production run of 100,000 chips, this NRE engineering cost becomes quite affordable.

The Cadence offering accelerates mixed-signal SoC design for IoT, incorporating the ARM IoT Subsystem for Cortex-M processors and Cadence’s interface IP and unified mixed-signal implementation solution, now optimized specifically for Cortex-M cores. The design flow integrates the Virtuoso custom design platform with the Innovus Implementation System, and the Spectre custom verification platform with the Incisive Enterprise Simulator provides the basis for ARM-based IoT design and verification.

These tools are not cheap, so further lower the barriers to the chip development, Cadence has also joined the ARM DesignStart program to provide low cost tools and IP for designs incorporating the Cortex-M0 processor. This offers potential chip designers access to free Cortex-M0 processor IP for design, simulation, and prototyping, with the option of then purchasing a simplified fast-track license for commercialization.

The ARM IoT Subsystem and DesignStart packages provide the most comprehensive solution a designer may need – including tools and IP – to accelerate time-to-silicon for their IoT applications.  The combined mixed-signal IoT flow for both the IoT subsystem package and DesignStart are available on the Cadence Hosted Design Solution (HDS), a software-as-a-service (SaaS) model which offers quick access to EDA tools, support and methodologies. With this secure solution, users can log in anywhere, anytime and gain access to tools without needing installation or the supporting hardware for it.

Optimizing IoT system design requires a deep understanding of tool flows, methodology, IP, packaging and software. ARM has developed a test chip to showcase this complete IoT implementation using a complete Cadence tool flow, the ARM IoT Subsystem and Cadence IP. The test chip includes processor IP, Artisan physical IP, wireless connectivity solutions, interface IP, software, design tools (both front- and back-end), optimized design methodology and scripts.

“ARM is seeing a growing demand for custom SoCs as our partners continue to focus on improving costs, power and functionality,” said Vincent Korstanje, vice president of marketing, systems & software group at ARM. “The collaboration with Cadence makes designing IoT platforms and custom SoCs even easier, further accelerating time to market.”

“We are collaborating with ARM to provide a complete solution of optimized IP, tool flows and subsystems to enable customers to deliver emerging Internet of Things applications,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer, Cadence. “Through our continued collaboration with ARM on both ARM DesignStart and the ARM IoT Subsystem for Cortex-M, we’ve optimized our EDA tools and methodology to complement ARM IP to bring designers from concept to silicon much faster.”

But Mentor is also joining the party through a similar collaboration using the Tanner AMS analogue/mixed-signal design flow for M0 processor-based implementations as part of the DesignStart program. The collaboration lowers the barriers to embedded and IoT device design and verification through a combination of an affordable, complete IC design tool suite and the ability to evaluate the design flow on a reference design at no cost.

“The free evaluation environment and an affordable tool suite from Tanner gives any vendor a fast and effective way to develop Cortex-M0 based smart analog mixed-signal designs,” said Nandan Nayampally, vice president of marketing and strategy, CPU Group at ARM. “Our partnership with Mentor Graphics will streamline the path to full production of IoT and embedded products, reducing developers’ costs and increasing their speed to market.”

The Tanner design flow supports digital, analogue, AMS, and MEMS design in a highly integrated, end-to-end flow. Designers capture the schematic, perform analogue and mixed-signal simulation, and lay out and verify the physical design. This design flow offers a complete, processor-based IoT chip environment.

Designers will be able to evaluate an ARM Cortex-M0 IoT reference design at no cost by using a web-based Mentor Virtual Lab to interact with the complete set of Tanner design tools. After evaluation, customers can easily purchase the specially-priced software from Tanner to begin creating their own IoT designs and combine this with the free Cortex-M0 design access available on the ARM DesignStart portal.

“The Tanner design flow is already very popular with IoT design companies,” said Greg Lebsack, general manager of the Tanner EDA business unit at Mentor Graphics. “By collaborating with ARM on DesignStart, we further strengthen our design flow by making it easy for AMS designers to include an ARM Cortex-M0 processor in their IoT designs.”

ARM of course wants to have more and more chip suppliers in the IoT. The new ARM Approved Design Partner program also provides DesignStart users with a global list of audited design houses for expert support during development.

The DesignStart portal offers SoC designers free access to ARM Cortex-M0 processor IP for design, simulation and prototyping with the option to buy a simplified and standardized $40,000 fast track license. The addition of Cadence and Mentor Graphics tools for DesignStart users accelerates the development of custom SoCs for embedded and Internet of Things (IoT) applications. With test chips from as little as $16,000 to manufacture (not inclusive of EDA tooling and IP licensing costs), the path to custom SoCs is now much easier.

“ARM’s DesignStart portal, with its convenient access to the Cortex-M0 package and its low-cost path to commercialization, is already making it easier for start-ups and OEMs to create embedded and mixed-signal SoCs,” said Nandan Nayampally, vice president of marketing and strategy for the CPU group at ARM. “Simplifying access to EDA tools from Cadence and Mentor Graphics will further spur rapid innovation, creating a fast path to production silicon for companies looking to deliver an embedded or connected IoT product.”

The Approved Design Partner program helps designers with the chip implementation. “The semiconductor industry has high expectations for future growth in the IoT space, with DesignStart ARM has taken a significant step towards enabling this growth and lowering entry barriers,” said Graham Curren, CEO at one design partner, Sondrel.