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Tuesday, May 24, 2011

Redpine moves to 3x3 MIMO for HD video over WiFi

BEAM450 chipset includes MIMO ML decoding, transmit beamforming and simultaneous dual-band for 450Mbit/s throughput

By Nick Flaherty www.flaherty.co.uk

Redpine Signals has developed a family of highly integrated semiconductor products conforming to the 802.11n standard that are the first MIMO chips to support "software configurable simultaneous dual-band." This patent pending feature enables the system integrators to re-configure the MIMO chipset on-the-fly from a 3-Spatial Stream 450Mbps 3x3 system (working in either 2.4GHz or 5GHz ISM bands) into a simultaneous dual-band system with 150Mbps in one band and 300Mbps in the other band.
Simultaneous dual-band enables robust QoS provisioning for demanding video applications in crowded wireless environments, and the Maxi-Fi® BEAM450 provides this at zero cost and power overhead to the system. The new Maxi-Fi products include the RS9330 802.11n Baseband chip interfacing to either the RS8330 (Dual-band MIMO Radio chip) or the RS8331 (Dual-band MIMO Radio chip with built-in high power-amplifiers).
Redpine also provides TURBO900 and TURBO1350 reference designs, which use two or three RS9330 chips respectively. These designs provide physical layer throughputs of 900Mbps and 1.35Gbps on a "single" PCI-e host interface, thus addressing the performance requirements of today's most demanding wireless video applications.
With CMOS integration of a high performance MAC, baseband processor, analogue front-end, crystal oscillator, calibration EEPROM, balun, dual-band RF transceiver and dual-band high-power amplifiers (RS8331 only), the chips are targeting high throughput and high QoS wireless applications such as HD video streaming, storage devices, wireless routers, broadband access modems, televisions, access points, and set-top boxes. The chipset maintains over 300Mbps of TCP data throughput on various host platforms and runs on the 802.11n MAC on an SoC based on Redpine's proprietary four-threaded processor (ThreadArch) with very low-host overhead.
The chipsets will be sampling in Q3-2011, with volume shipment scheduled for Q1-2012.

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