SEGGER gives BBC Micro:bit commercial boost

By Nick Flaherty www.flaherty.co.uk


SEGGER has introduced J-Link support for the low cost BBC micro:bit embedded board providing developers a path to using a production grade IDE for their next project.

SEGGER offers the capability to upgrade the firmware on the BBC micro:bit DAPLink to a J-Link OB (On Board). This firmware makes the on-board debug solution on the BBC micro:bit compatible to J-Link, allowing users to take advantage of all J-Link features such as ultra fast flash download and debugging speeds and the free-to-use GDBServer as well as application development using an IDE.

“Adding J-Link debug capabilities to the BBC micro:bit broadens its exposure to an even larger audience. The micro:bit eco-system is improved significantly by making professional tool options available to developers,” says John Leonard, Product Marketing Manager at Nordic Semiconductor.

J-Link is supported in all major IDE’s; IAR EWARM, Keil MDK, Rowley Crossworks, SEGGER’s own Embedded Studio and other Eclipse/GDB based offerings. This gives students and developers flexibility in their choice of IDE.

The SEGGER J-Link is the most popular family of debug probes on the market. It is tool chain independent and works with free GDB-based tool chains such as Embedded Studio, and Eclipse, as well as commercial IDEs from: Atmel, Atollic, Coocox, Cosmic, Freescale, IAR, KEIL, Mentor Graphics, Microchip, Phyton, Rowley, Renesas, Tasking and others. With the J-Link family, investments in the debug probe are preserved when changing compiler or even CPU architecture.

J-Link supports multiple CPU families, such as ARM 7, 9, 11, Cortex-M, Cortex-R, Cortex-A as well as Renesas RX100, RX200, RX600 and Microchip PIC32; there is no need to buy a new J-Link or new license when switching to a different yet supported CPU family or tool-chain. SEGGER is also continuously adding support for additional cores, which in most cases, only requires a software/firmware update and unlimited free updates are included with even the baseline model of the J-Link family. All J-Links are fully compatible to each other, so an upgrade from a lower-end model to a higher-end model is a matter of a simple plug-and-play.

Full product specifications are available at: www.segger.com/jlink.html

For more information on J-Link OB for BBC micro:bit go to: https://www.segger.com/bbc-micro-bit.html

Key deal sees access to the heart of an SoC for embedded debug

By Nick Flaherty www.flaherty.co.uk

UltraSoc integration enables vendor-independent debug within industry standard toolchain

A key deal for embedded chip designers and developers sees UltraSoC and Lauterbach collaborating on a powerful, fully-featured independent system-on-chip (SoC) development and debug environment. 

Combining Lauterbach’s TRACE32 integrated, universal development system with UltraSoC’s on-chip debug and analytics IP has the potential to dramatically ease the work of engineering teams creating the advanced SoCs needed in industries as diverse as mobile communications, automotive and the Internet of Things (IoT).

Today’s silicon chips can incorporate over a billion transistors and are constructed from many tens of different functional blocks, mixing purchased processor cores, IP re-used from previous designs, and custom logic developed by the design team itself; they also run substantial amounts of software. This complexity makes it very difficult to understand the behavior of the complete system when it is finally pieced together – even for the engineers who designed and developed it. This in turn can lead to chips that do not deliver the expected performance, or contain hard-to-find bugs, leading to significant extra engineering costs, products that miss their market window, and occasionally even field failures. UltraSoC and Lauterbach’s collaboration addresses these problems.

TRACE32 is a set of modular embedded development tools with integrated debug environments that support all of the processor architectures commonly used in the market today. UltraSoC’s IP works inside the SoC itself, monitoring and analyzing the real-world behavior of any on-chip structure – and the device as a whole – non-intrusively and at wire speed. Together, TRACE32 and UltraSoC’s IP give design teams complete visibility of the real-world behavior of their devices – vital in the debugging process which can consume up to half of the total development effort for a typical SoC.

“The combination of TRACE32 and UltraSoC is a powerful one," said Norbert Weiss, head of sales and marketing at Lauterbach. "This allows users of our tools to gain an intimate understanding of the behavior of the whole of the SoC, including all the on-chip structures such as busses and custom logic, in addition to our existing support for all of the common embedded processors. UltraSoC’s message-based on-chip infrastructure and high-speed external interface capabilities – USB for example – open up a range of new possibilities for users of our development tools.”

The TRACE32 debug tools provide quick, effective debugging for more than 80 processor architectures, with full support for the entire debug process, including run control, OS-support, multicore debugging and on-chip trace. The debugger supports multiple programming languages, most compilers and hosts, and a broad variety of multicore architectures. Interfacing the UltraSoC on-chip debug and analytics fabric with TRACE32 gives users full control over the debug features of UltraSoC’s silicon IP, and full access to the information generated by the company’s range of on-chip monitors and analytics engines.

As well as connecting externally with the debug host, the UltraSoC architecture includes an on-chip message-based interconnect, and allows monitoring of any third party processor core, bus or custom logic block. This ability to create a holistic, overarching development and analytics solution is key to solving the tricky problems posed by heterogeneous multi-core SoCs running complex software.

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UltraSoC adds deadlock detection to its SoC analysis, debug and profiling tools

By Nick Flaherty www.flaherty.co.uk

One of the biggest challenges with developing software for embedded systems is deadlocks, where processors hang or stall as a result of complex interactions of the data. While this is traditionally tackled at the board level with a probe and logic analyser, it's a nightmare when the system is all inside a chip. So when Cambridge-based tool developer UltraSoC adds deadlock detection capabilities into its embedded system-on-chip (SoC) analysis, profiling and debug, it's a big thing. The new analysis features allow embedded SoC architects, developers and debug engineers to detect and diagnose those hard-to-find corner cases which can cause complex SoCs to hang or stall intermittently and unpredictably, sometimes after days of continuous normal operation. “Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs,” said Gadge Panesar, chief technology officer of UltraSoC. “These conditions are a major contributor to the current crisis in the SoC industry. Conventional approaches either ignore the problem, or attempt to deal with it by generating massive, unmanageable data sets. UltraSoC takes a smarter approach, focusing on generating meaningful, actionable information; for the first time chip design teams can truly understand the behaviour of today’s complex SoCs.” Bus deadlocks occur when a processor is waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives. Traditionally, the only way of isolating such problems has been to attempt to continuously trace and output all bus activity, requiring a high-bandwidth off-chip connection to gather the data, and difficult offline analysis software of huge data-sets. The UltraSoC technology uses a “smart” on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem. This allows chip designers to efficiently and intelligently “look inside” their products, at wire speed, during normal operation, rather than having to pull out a trace of all the activity and go over millions of data points. The new deadlock detection capabilities are targeted at particularly difficult conditions that can cause devices to fail intermittently and unpredictably, including bus and software deadlocks. Software deadlocks are increasingly common in today’s SoCs. In a typical scenario, two different software processes might use a locking mechanism to govern shared access to common on-chip resources: for example another core, hardware peripherals or the capabilities of another software process. Problems can arise when each CPU believes that the other has locked its access to the shared resources. In this case UltraSoC provides an on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important. A key advantage is that UltraSoc is not tieed to any one architecture, supporting many different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others), making it possible to solve these situations. SoC debug and silicon validation are key challenges facing the global electronics industry today. UltraSoC’s technology creates an on-chip debug infrastructure that enables pre- and post-silicon debug, reducing the risks in chip design, improving time-to-market, increasing quality and reducing costs. www.ultrasoc.com