USB3.0 test chip from TI

Texas Instruments has developed a new 5Gbit/s transceiver test chip designed to the USB3.0 specification version 1.0 as part of the SuperSpeed USB promoters group. The new transceiver is capable of driving and receiving signals over 4m USB3.0 cables to ensure data integrity. This transceiver will be demonstrated at the USB Developers Conference in Tokyo, Japan on May 21-22.
The new SuperSpeed USB transceiver, with intellectual property (IP) for a digital controller from design tool vendor Synopsys, tested successfully at the USB-IF SuperSpeed Peripheral Interoperability Lab.

“Demonstrating interoperability between Synopsys’ DesignWare SuperSpeed USB digital controller and TI’s USB transceiver gives designers confidence that the IP functions successfully in a real-world system environment,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “Synopsys and TI are working together to help advance new technology into the market quickly, while minimizing risk and speeding time-to-market.”

The test chip includes an integrated spread spectrum PLL, support for multiple input reference frequencies: 20 MHz, 25 MHz, 30 MHz and 40 MHz, PIPE3 and ULPI compliant interfaces and programmable transmitter pre-emphasis. These save system cost by eliminating the need for an external spread spectrum clocking device and give interoperability across a wide selection of ASIC / FPGA platforms eases designs by allowing designers to work with the same USB device, regardless of the processor platform.

The first of TI's SuperSpeed USB family of devices, the TUSB1310, SuperSpeed USB transceiver, will sample by the end of the year with volume production in the first quarter of 2010


USB3.0

The most obvious change in SuperSpeed USB versus USB 2.0 high-speed is the over 10X speed increase from 480 Mbps to 5 Gbps. There are many applications for which the USB connection is becoming the bottleneck and, as with the introduction of USB 2.0 high-speed, SuperSpeed USB will inspire the creative minds in the industry to develop new, emerging applications and end-equipment that will benefit from the higher performance. The 5Gbit/s data rate should provide headroom for the next 5 years.

In addition to the increase in speed, the physical layer electrical signaling has changed from the simple two-wire system to a dual-simplex data path. This is done over a completely different set of connections than the existing USB 2.0 two-wire interface, which remains untouched. In addition, it was mandatory that the any changes in the electrical signaling scheme NOT drive the need for a new forma factor plug or receptacle on the host, and if possible, on the peripheral as well. In order to minimize the risk, the promoters group determined that creating the new signaling scheme to be very similar to PCI Express could meet the goals. This also allows the connection to retain sideband functionality without additional wires and allow for receiver termination for connect/disconnect detection.

One of the other key changes was to focus on improving the power efficiency of the bus. This is ideal for extending the battery life for portable devices, whether hosts (notebook PCs) or peripherals. The specification defines excellent power characteristics, especially for idle links. Both Upstream and Downstream ports can initiate lower power states of the link. There is also local power management control using multiple link power states defined to further improve the power use efficiency. In addition, another power saving method was to eliminate all polling of devices.