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Wednesday, November 29, 2017

64bit RISC-V core targets data centre chips

By Nick Flaherty

Codasip in the Czech republic has developed its first 64bit version of the RISC-V instruction set, aiming the IP at datacentre chip designs

The Bk5-64 at the top end means Codasip now offers customers a wide range of cores down to the ultra-low-power zero-stage Bk1. All Berkelium processors are generated via the unique Codasip Studio customisation tool, allowing for fast configuration and optimisation of the cores.

“With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” said Karel Masařík, founder and CEO of Codasip. “By introducing the Bk5-64, Codasip is addressing the need for affordable 64-bit embedded processors, complete with a state-of-the-art LLVM-based software development toolchain with advanced profiling.”

RISC-V is an open, free instruction set architecture (ISA) that a number of developers are using for embedded cores. We'll follow up on details of the BK5-64 core later in Q4 2017.

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