NXP Semiconductors has developed a family of high-performance safe microprocessors to control vehicle dynamics in next-generation electric and autonomous vehicles based around the ARM Coretex R52 core that includes four separate processing paths for redundancy and safety.
The new NXP S32S microprocessors will manage the systems that accelerate, brake and steer vehicles safely, whether under the direct control of a driver or an autonomous vehicle’s control.
“We see that the shift to next-generation autonomous and electric vehicles is introducing huge challenges to carmakers,” said Ian Riches, executive director in the Strategy Analytics Global Automotive Practice. “Not least of these is the ability to get silicon in hand fast enough and with enough performance headroom to ease the transitions to autonomous and advanced HEV/EV. A car can be extremely intelligent, but if it can’t act safely on a decision, you don’t have a reliable autonomous system at all.”
At 800MHz the first of the new S32 product lines, the S32S microprocessors offer the highest performance ASIL D capability available today.
The NXP S32S processors use an array of the new Arm Cortex-R52 cores, which integrate the highest level of safety features of any Arm processor. The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new “fail availability” capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.
Hypervisor
“We see that the shift to next-generation autonomous and electric vehicles is introducing huge challenges to carmakers,” said Ian Riches, executive director in the Strategy Analytics Global Automotive Practice. “Not least of these is the ability to get silicon in hand fast enough and with enough performance headroom to ease the transitions to autonomous and advanced HEV/EV. A car can be extremely intelligent, but if it can’t act safely on a decision, you don’t have a reliable autonomous system at all.”
At 800MHz the first of the new S32 product lines, the S32S microprocessors offer the highest performance ASIL D capability available today.
The NXP S32S processors use an array of the new Arm Cortex-R52 cores, which integrate the highest level of safety features of any Arm processor. The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new “fail availability” capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.
Hypervisor
NXP has worked with OpenSynergy to develop a fully featured, real-time hypervisor supporting the S32S products. OpenSynergy’s COQOS Micro SDK is one of the first hypervisor platforms that takes advantage of the Arm Cortex-R52’s special hardware features. It enables the integration of multiple real-time operating systems onto microcontrollers requiring high levels of safety (up to ISO26262 ASIL D). Multiple vendor independent OS/stacks can also run on a single microcontroller. COQOS Micro SDK provides secure, safe and fast context switching ahead of today’s software-only solutions in traditional microcontrollers.
A companion ASIL D safety system basis chip, the FS66 functionally safe multi-output power supply IC, is also available, along with integrated flash memory up to 64Mbytes supporting on-the-fly, over-the-air update capability with zero processor downtime. A user programmable hardware security engine with private and public key support and a version is available with a PCIe interface for ADAS domain supervisory applications.
“When we started the development of the S32S it was clear that just building another incremental microcontroller was not what customers needed to handle the safety and performance requirements of next-generation and autonomous vehicles,” said Ray Cornyn, vice president of Vehicle Dynamics and Safety. “Our new safety processors leverage the high performance multi-core benefits of the S32 Arm platform while still supporting traditional microcontroller ease of use and environmental robustness.”
S32S will be sampling in Q4 2018 to NXP’s Automotive Alpha customers.
A companion ASIL D safety system basis chip, the FS66 functionally safe multi-output power supply IC, is also available, along with integrated flash memory up to 64Mbytes supporting on-the-fly, over-the-air update capability with zero processor downtime. A user programmable hardware security engine with private and public key support and a version is available with a PCIe interface for ADAS domain supervisory applications.
“When we started the development of the S32S it was clear that just building another incremental microcontroller was not what customers needed to handle the safety and performance requirements of next-generation and autonomous vehicles,” said Ray Cornyn, vice president of Vehicle Dynamics and Safety. “Our new safety processors leverage the high performance multi-core benefits of the S32 Arm platform while still supporting traditional microcontroller ease of use and environmental robustness.”
S32S will be sampling in Q4 2018 to NXP’s Automotive Alpha customers.
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