SiFive has used the RISC-V instruction set for what is says is the world's smallest embedded 64bit processor core.
The S2 core IP series is a configurable core that can be as small as 13.500 gates in the RV32E 32bit version, but has not released the size of the S21 embedded core. This has separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs).
Edge chips face a wide range of requirements of real-time latency, deterministic capability and stringent power constraints. The S2 enables SoCs to have an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices. The 2 Series can be configured to be as small as just 13,500 gates (in RV32E form) and the S2 is just half the size of a similarly configured S5 core.
Security is enhanced by separation between secure and non-secure domains. This degree of flexibility is what is needed to meet the constraints in terms of power, area and real-time demands as well as the requirements in terms of performance of modern edge workloads and applications. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores via SiFive’s Core Designer.
“SiFive’s 64-bit S Cores bring their hallmark efficiency, configurability and silicon-proven Core IP expertise to 64-bit embedded architectures,” said Ted Speers, head of product architecture and planning at Microchip Technology’s Microsemi subsidiary and RISC-V Foundation board member. “The S Cores will enable innovation for the next generation of embedded compute.”
The ever-growing number of connected devices with artificial intelligence, machine learning, IoT, and real-time workloads have generated a massive demand for greatly enhanced embedded intelligence in compute at the edge.
“SiFive’s 64-bit S Cores bring their hallmark efficiency, configurability and silicon-proven Core IP expertise to 64-bit embedded architectures,” said Ted Speers, head of product architecture and planning at Microchip Technology’s Microsemi subsidiary and RISC-V Foundation board member. “The S Cores will enable innovation for the next generation of embedded compute.”
The ever-growing number of connected devices with artificial intelligence, machine learning, IoT, and real-time workloads have generated a massive demand for greatly enhanced embedded intelligence in compute at the edge.
Legacy architectures have long ignored the need for small, efficient, 64-bit, real-time embedded processors says SiFive, which has secured more than 25 design wins for the 2 Series Core IP alone since its launch at DAC in June 2018.
The S2 has no direct competitive equivalent, it says, providing easier integration than 32-bit physical addressing and provides the benefit of fast and efficient access to slow or far-away memories via flexible memory maps and micro instruction caches.
“To achieve SiFive’s mission to democratize silicon and compute, we must rapidly enable embedded intelligence where data touches the real world,” said Yunsup Lee, CTO and co-founder, SiFive. “SiFive recognized a deep need for a full 64-bit embedded solution. We leveraged our unique methodology to rapidly innovate and architect 64-bit, fully heterogenous and coherent, real-time core capability. Our S2 Core IP Series is silicon proven and brings efficiency, performance, and security to enable greater innovation at the edge.”
www.sifive.com.
“To achieve SiFive’s mission to democratize silicon and compute, we must rapidly enable embedded intelligence where data touches the real world,” said Yunsup Lee, CTO and co-founder, SiFive. “SiFive recognized a deep need for a full 64-bit embedded solution. We leveraged our unique methodology to rapidly innovate and architect 64-bit, fully heterogenous and coherent, real-time core capability. Our S2 Core IP Series is silicon proven and brings efficiency, performance, and security to enable greater innovation at the edge.”
www.sifive.com.
No comments:
Post a Comment