It used to be thought that VLIW (very long instruction word) compute engines were hard to program and not really for the embedded market, but Cadence Design Systems is using it to span a wide range of applications from automotive to the Internet of Things (IoT).
The latest Tensilica DSP core, the Fusion G3, (above) can be programmed in C or C++ rather than a separate DSP tool chain, to integrate audio, imaging, communications, sensor and embedded DSP in a wide range of applications from radar in cars to natural language interfaces in IoT.
The Tensilica Fusion G3 DSP is built on the existing Xtensa real-time control processor and has a flexible memory subsystem, optional integrated DMA controller and memory protection unit (MPU).
It is a hefty beast, based around a 128-bit, 4-slot VLIW architecture with a high performance 11-stage DSP pipeline with with quad 32-bit integer MACs and quad single precision 32-bit floating point Fused Multiply Adds (FMAs) or MACs.
The Tensilica Fusion G3 DSP is built on the existing Xtensa real-time control processor and has a flexible memory subsystem, optional integrated DMA controller and memory protection unit (MPU).
It is a hefty beast, based around a 128-bit, 4-slot VLIW architecture with a high performance 11-stage DSP pipeline with with quad 32-bit integer MACs and quad single precision 32-bit floating point Fused Multiply Adds (FMAs) or MACs.
This provides up to 24GLFLOPS@1GHz for compute-intensive applications such as mid- to high-end audio pre and post processing, radar and low end image processing. The power consumption will of course depend on the process technology and clock speed.
"“As we continue to broaden our customer base, we are solving a wider range of SoC challenges for customers running a diverse set of software applications,”" says Steve Roddy, senior group director of product marketing for Tensilica in the IP Group at Cadence. “
Auto-vectorization and extensive library support gets around some of the problems of programming a VLIW engine, and the C and C++ support means engineers with extensive floating-point performance requirements can quickly port existing code to the Fusion G3 with the optional Vector Floating-Point unit.”
“Cadence has long supplied function-specific DSPs for audio, imaging/vision and baseband signal-processin, but fast-evolving markets like automotive and IOT mean a narrowly-focused DSP is not always the best choice,” said Mike Demler, senior analyst of The Linley Group. “This is creating an emerging demand for a high performance, multi-purpose DSP which supports a wider range of data types and operations, including both fixed and floating point, that can handle many different signal processing tasks, he says.
“Cadence has long supplied function-specific DSPs for audio, imaging/vision and baseband signal-processin, but fast-evolving markets like automotive and IOT mean a narrowly-focused DSP is not always the best choice,” said Mike Demler, senior analyst of The Linley Group. “This is creating an emerging demand for a high performance, multi-purpose DSP which supports a wider range of data types and operations, including both fixed and floating point, that can handle many different signal processing tasks, he says.
The Fusion G3 DSP was co-designed with a lead customer and has already been taped out in silicon earlier this year. It will be available for broader licensing in October 2016.
Tensilica processors have been licensed by 17 of the top 20 semiconductor vendors, have over 250 licensees, with thousands of different cores in silicon. The Xtensa architecture is one of the most popular licensable processor architectures, shipping over 3bn cores in 2015, in products spanning sensors to supercomputers.
Tensilica processors have been licensed by 17 of the top 20 semiconductor vendors, have over 250 licensees, with thousands of different cores in silicon. The Xtensa architecture is one of the most popular licensable processor architectures, shipping over 3bn cores in 2015, in products spanning sensors to supercomputers.
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