Eating into the MIPS business, embedded motor and motion control chip maker Trinamic has selected the Bk3 processor from Czech designer Codasip for its next designs. The Bk3 is based on the open source RISC-V architecture.
German Trinamic’s products serve multiple markets including laboratory and factory automation, semiconductor manufacturing, textiles, robotics, ATMs, and vending machines – wherever reliable positioning is required such as 3D printing, medical pumps, and security cameras.
“We chose RISC-V as the microcontroller platform for our future motion control product families. The open source character of the instruction set ensures the longevity our customers require,” stated Jonas P. Proeger, Marketing Director of Trinamic. “After investigating alternatives, we determined that Codasip’s Bk3 offered the ideal combination of performance and power efficiency that our applications demand. Backed by best-in-class development tools and the RISC-V ecosystem, the Bk3 is perfect for our future processing needs”.
The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.
www.trinamic.com and www.codasip.com
German Trinamic’s products serve multiple markets including laboratory and factory automation, semiconductor manufacturing, textiles, robotics, ATMs, and vending machines – wherever reliable positioning is required such as 3D printing, medical pumps, and security cameras.
“We chose RISC-V as the microcontroller platform for our future motion control product families. The open source character of the instruction set ensures the longevity our customers require,” stated Jonas P. Proeger, Marketing Director of Trinamic. “After investigating alternatives, we determined that Codasip’s Bk3 offered the ideal combination of performance and power efficiency that our applications demand. Backed by best-in-class development tools and the RISC-V ecosystem, the Bk3 is perfect for our future processing needs”.
The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.
www.trinamic.com and www.codasip.com
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