STMicro brings SMP ARM multicore to embedded

Symmetrical ARM Cortex multiprocessor architecture with DDR3 delivers cost efficiency, computing power and customizability for multiple embedded applications 

By Nick Flaherty www.flaherty.co.uk

STMicroelectronics has launched a new multicore processor architecture that will be the backbone for the new members of its popular SPEAr (Structured Processor Enhanced Architecture) family of embedded microprocessors, targeting high-performance connectivity and embedded applications.
Leveraging its experience of the production-proven SPEAr300 and SPEAr600 lines, the new SPEAr1300 product line couples dual ARM Cortex-A9 processors with a DDR3 memory interface and is manufactured in ST’s low-power 55nm HCMOS (high-speed CMOS) process technology. 
The  dual ARM Cortex-A9 processors support fully symmetrical operation, at speeds  up to 600MHz/core for 3000 DMIPS equivalent.
The SPEAr1300 makes use of ST’s innovative Network-on-Chip technology for internal peripheral interconnect, assuring support for multiple different traffic profiles, while maximizing data throughput in the most cost-effective and power-efficient way. Initial sampling has already started to early adopters.

The new architecture offers industry-leading performance in terms of DMIPS/MHz and power consumption/DMIPS ratios, in addition to cost efficiency and customizability advantages. The availability of integrated DDR3 memory controller and a full set of connectivity peripherals like PCIe, SATA, USB and Ethernet, among other features, make the SPEAr1300 the ideal choice for high-performance applications including networking, thin client, videoconferencing, NAS (Network-Attached Storage), computer peripherals, and factory automation.

“This new architecture for the SPEAr family builds upon the unrivalled low power and multiprocessing capabilities of the ARM Cortex-A9 processor core” said Loris Valenti, General Manager of ST’s Computer Systems SoC Division. “Upcoming SPEAr embedded microprocessors will deliver an unprecedented combination of processing performance, memory throughput, flexibility and low power for next-generation connectivity appliances.”

Key features:

• Dual ARM Cortex-A9 cores, running at 600MHz for 3000 DMIPS equivalent
• 64-bit AXI (AMBA3) bus Network-on-Chip technology
• DRAM and L2 cache with Error Correction Code (ECC)
• 533MHz 32-bit DDR3 memory controllers with ECC; 16-bit DDR2 also supported
• Accelerator coherence port
• Gigabit Ethernet
• PCIe 2.0 supporting 5 GT/s (Gigatransfers/second)
• SATA II 3 Gbit/s
• USB 2.0
• 256-bit key hardware encryption/decryption
• 1.3 million gates of configurable logic

Embedded microprocessors from the new SPEAr1300 product line will be announced over the next few months, expanding ST’s SPEAr family and providing an extensive choice for leading customers.

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ST moves to 32nm for networking chips

By Nick Flaherty www.flaherty.co.uk

Industry’s first Serializer-Deserializer (SerDes) IP in 32nm demon to customers 

STMicroelectronics has launched a 32nm technology platform for the design and development of leading-edge application-specific integrated circuits (ASICs) for networking applications. Central to the new 32nm SoC design platform, which implements ST’s 32LPH (Low-Power High-performance) process technology, is the industry’s first Serializer-Deserializer (SerDes) IP available in 32nm ‘bulk’ silicon.
Enabling very large ASIC designs, greater than 200mm², ST’s new 32nm 32LPH ASIC design platform enables an unprecedented mix of high performance, high complexity, low power consumption and reduced silicon real estate per functional block. The platform is designed to accelerate the development of next-generation networking ASICs used in high-performance applications such as enterprise switches, routers and servers as well as optical cross-connect and wireless infrastructure applications.
“With the introduction of the 32LPH platform, ST is enabling the next generation of equipment for communication infrastructure applications, which requires highly integrated ASICs that can satisfy the increasing demand in performance, while also meeting extremely challenging power consumption and silicon integration goals,” said Riccardo Ferrari, Group Vice President and General Manager of ST’s Networking and Storage Division. “We are extremely encouraged by the strong interest that customers are demonstrating for this platform, which has already gained key design wins.”

ST’s SerDes IP, called S12, is a key piece of intellectual property that has already been successfully demonstrated in labs at selected key customers. The S12 IP is vital for the development of ASICs for networking applications and enables chip-to-chip, chip-to-module and backplane communications in networking equipment designs.
“ST is the first silicon supplier to bring a full design platform in a 32nm bulk-silicon process technology to the communication infrastructure market, including a next-generation predictive ASIC top-down design methodology, together with a full set of proven IP, such as a SerDes and embedded DRAM, successfully developed over many years by ST in previous technology nodes,” said Philippe Magarshack, Technology R&D Group Vice-President, Central CAD & Design Solutions GM, STMicroelectronics. “ST’s Technology R&D center in Crolles, France, has been instrumental in accelerating the completion of the 32LPH platform where low-power technology meets the high-performance requirements of networking applications, while still enjoying all the cost benefits of high-volume manufacturing. In addition, we have partnered with selected EDA vendors to offer networking customers the benefits of a predictable ASIC turnaround time, including fast virtual physical prototyping, and 32nm-class timing, signal and power integrity sign-off.”
The first ASIC prototypes implemented in ST’s 32LPH process technology are expected early in 2011 with production ramp-up in the second half of 2011.
Further Technical Information
ST’s 32LPH (Low-Power High-performance) design platform for networking applications supports up to 10 metallization layers to increase routing efficiency. The platform is based on the 32nm High-K Metal Gate process developed within the framework of the ISDA alliance, but also incorporates specific IP and devices from ST, such as embedded DRAM with 10-Mbit per square millimeter density and Ternary Content Address Memory (TCAM).
A SerDes (Serializer-Deserializer) is normally integrated multiple times (often up to 200) in a single ASIC chip. It enables serial communication between:

• ICs, or ASICs, on the same electronic printed-circuit board (Chip-to-Chip);
• ASICs and the Optical Module, which links to remote equipment (Chip-To-Module);
• ASICs and Physical Interface Module (Chip-To-Module); or
• ASICs and the system backplane - the backplane is the internal physical rack inside equipment in which all the system cards are mounted.

ST’s S12 IP macro, which is based on ST’s proven SerDes architecture, can be scaled up to eight 12.5-Gbit/s transmit/receive (Tx/Rx) channels per macro. The S12 has been designed with an optimal footprint for flip-chip BGA packages, and will soon be followed by ST’s S14 IP, which can reach up to 14-Gbit/s transmission speed.

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STMicro launches first EAL6+ high security smartcard controller

Supports latest security protocols and enhanced contact/contactless operation, surpass credentials of competing components

STMicroelectronics has announced details of its formal EAL6+ Common criteria certification - the highest security standard applicable - for its ST23YR80 secure dual microcontroller including its optional crypto libraries.
ST's chip is the world's first secure microcontroller to achieve EAL6+ according to the Common Criteria 3.1 methodology. Other processors have been accredited at lower levels or using less stringent methodologies. ST applied formal methods, which guarantee all states and transitions are known, from the beginning of the processor's design, resulting in formally proven high security with optimal ease of use and efficiency. The EAL6+ certified device is capable of completing a secure passport transaction in less than 3 seconds using secure embedded software from Sagem Securite, a hi-tech company in the Safran Group, called IDeal Pass, which is the fastest competitive solution certified to EAL5+. This is vital not just for obvious high secuirty applications such as passports, but also for medical cards and increasingly for bank cards.
Practical benefits will include high productivity and security at border controls and short wait times for travelers. All e-passport norms are supported, including Basic Access Control (BAC) and Extended Access Control (EAC) using the highest crypto-key length. In addition, the ST23YR80 obtained a Certificate of conformity to ISO/IEC 14443 standard from SOLIATIS LAB: Reference SL.E.CER.0912.001.

Key features of the ST23YR80:
-- Enhanced crypto-processor NESCRYPT
-- Optional full feature certified crypto library
-- High CPU clock frequency
-- Dense on-chip memories:
-- 80 Kbytes EEPROM
-- 390 Kbytes user ROM
-- 8Kbytes of Ram
-- Enhanced contactless performances using ISO14443 type B interface

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Top 15 most admired semiconductor companies in 2010

Fortune magazine has listed its most admired companies in the world, with a separate break-out for semiconductor companies.

Among semiconductor companies evaluated, STMicroelectronics is ranked the 6th most admired, in its first year as a participant in the survey. Additionally, it is the highest-ranking Europe-based chipmaker on the list.

The “World’s Most Admired Companies” survey debuted in the U.S. in 1983 and began ranking companies worldwide in 1997. Companies are rated by their peers based on nine factors including quality of products or services, quality of management, global competitiveness, and soundness of financial position to name a few. 
This year approximately 4,170 top executives, directors, and financial analysts assessed companies in their own industries, and voted on companies being considered for the overall most admired list. A total of 667 companies from 33 countries across 55 industries were surveyed.

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STMicro turns to Mentor for 32nm design

Mentor Graphics is teaming up with STMicroelectronics on a broad collaboration to develop advanced design solutions at 32nm and down to 20nm.

The three-year joint-development project, named DeCADE, seeks to build on advanced design solutions for SoC (System On Chip) development for Digital and Analog design, including system-level approaches, design methodologies, place and route strategies, optical correction for advanced manufacturing, modeling, electrical characterization and parasitic extraction. ST will significantly contribute to the development of these new SoC design tools, which will give ST a head start in its ability to deliver customer-focused semiconductor chips and platforms.
DeCADE will provide design solutions for core CMOS technologies as well as for value-added and application-specific derivative technologies that are developed from the core CMOS process. These projects can make a fundamental difference in chip capability and, performance, as well as in system-solution cost; among the value-added derivative technologies being considered by the DeCADE projects include RF (Radio Frequency) and wireless technologies, as well as 3D Packaging and chip stacking technologies. As a recognized pioneer in these technologies, ST’s participation will assure the strength of the design solutions’ foundation and ensure that its next-generation tools contribute to its maintaining product and technology leadership.

"This joint development effort will provide ST with tools to develop state-of-the-art Systems-on-Chips (SoCs) at 32-nm and below for ST's customers, taking full advantage of the strong Silicon Process, Device Modeling and Design know-how present on the Crolles Site," said Philippe Magarshack, STMicroelectronics General Manager of Central CAD & Design Solutions. "This ST-Mentor Graphics joint effort further reinforces the Crolles cooperative R&D cluster, which already gathers partners that develop and enable low-power SoCs and value-added application-specific technologies and is a great example of a project developed within the framework of the Nano2012 program." This is a strategic R&D program, led by ST, which gathers research institutes and industrial partners and is supported by French national, regional and local authorities. The program aims to create one of the world's most advanced R&D clusters for the development of new generations of semiconductor technology platforms at the nano-electronic level
“As a leading provider of semiconductor based solutions, ST is an excellent partner with whom to explore and develop the design methodologies that the market will need over the next decade," said Greg Hinckley, President of Mentor Graphics. “We look forward to this collaboration as a further extension of Mentor Graphics efforts with our long term customer ST.”

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STMicroelectronics Launches 32bit Cortex-M3 line under $1

Optimized features for price-sensitive consumer, appliance and industrial designs from 85c

Taking the different approach from packing features into a device, STMicroelectronics has launched a 'value line' low cost version of its STM32 microcontroller.

Until now, engineers upgrading legacy 16-bit designs for higher performance and flexibility have had to choose from high-end alternatives that are featured for more complex applications. ST’s new STM32 Value Line remedies this by combining a 24MHz ARM Cortex-M3 processor core with peripheral features optimized for typical 16-bit applications such as home-entertainment products, appliances, and industrial equipment. At 24MHz with zero wait state embedded Flash memory access, the STM32 Value Line delivers up to 30 DMIPS, outperforming most of the 16-bit processors. The added advantage of its industry-standard processor, available in devices priced under $1, provides access to a large base of development knowledge and tools.

 Application-focused features embedded in the STM32 Value Line include up to 12 16-bit timers, including a PWM timer for motor-control applications. As many as 26 timer channels are available, with package options providing up to 100 pins, as well as a 12-bit high-speed Analog-to-Digital Converter (ADC), to solve a wide range of industrial control challenges. ST is also offering free software support, including a complete 3-phase motor-control library for appliance and motor-control applications and free VDE-certified libraries to help household appliances achieve necessary approval to EN/IEC60335-1 Class B.

The family also embeds hardware support for the Consumer Electronics Control (CEC) protocol included in the HDMI standard, thereby simplifying CEC implementation in products such as TVs, Blu-ray players, PVRs and home cinema equipment. CEC allows up to 10 HDMI devices to discover each other and communicate to manage user-convenience features such as one-touch control of multiple devices via a single remote. Implementing CEC in hardware also frees the processor core to perform extra high-level functions, thereby adding further value to developers’ applications.

In addition, a 12-bit Digital-to-Analogue Converter (DAC) allows developers to add audio support in a variety of applications such as security devices or home automation systems, and to address wider opportunities requiring analogue waveform generation and control.

The STM32 Value Line links developers into ST’s extensive STM32 family, which now contain five product lines presenting a choice of cost-sensitive, power-sensitive, connectivity-oriented or high-performance microcontrollers. In all, over 110 devices are available, offering a range of features and on-chip memory densities while maintaining pin and software compatibility across all devices. This commonality simplifies strategic processor platform selection by enabling convenient scaling and upgrading of designs, and allowing re-use of intellectual property and development tools to minimize cost and time to market for new products.

The STM32 Value Line microcontrollers are now sampling to lead customers. Volume production will begin from March 2010, at prices from $0.85 for 16Kbyte devices in 48-pin LQFP48 package and $1.44 for 64Kbyte devices in the 64-pin LQFP64 package, for quantities of 10,000 units.