Graceful degradation in encoding

An interesting element of the recent launch of a family of SD video codec cores from ARC is the use of 'graceful degradation' in the encoding process.
Depending on the resources available - and that can be power or memory - the cores can throw out various tools and reduce the quality of the encoding to extend the battery life or the recording time - this is all up to the designer and allows systems based on the cores to be differentiated through these engineering tradeoffs.

The five cores are based on the recently introduced VRaptor Multicore Architecture, each is programmable, encodes and decodes a wide range of popular video standards, and comes with optimized media processing elements including:
o Up to two 128-bit SIMD Media Processors
o A dual-channel media-optimized DMA engine
o Separate multi-standard encoding and decoding accelerators
o Programmable motion estimation accelerator
o SoC development tools
o Optimized video codecs:
o (encoders) H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, and JPEG
o (decoders) H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, VC-1 SP, MPEG-2 MP, MJPEG, JPEG, GIF, TIFF, and PNG



All this is very interesting when video becomes a key IP block for the next decade.