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Wednesday, October 05, 2011

ST teams with MIT on ultra low power microcontroller well under 1mW

System-on-Chip for Implantable Medical, Wireless Sensor Networks and Mobile Applications
By Nick Flaherty

STMicroelectronics and the Microsystems Technology Laboratories (MTL) of Massachusetts Institute of Technology have been working on an advanced R&D project targeting a low-power 32bit microprocessor technology that would give a core operating power consumption under 1mW at 100MHz.
Implemented in ST’s 65nm CMOS process, the ST-MIT microprocessor SoC reduces power consumption to 10.2 pJ/cycle at 0.54 V, while the SRAM memory cells can operate at 0.4 V. Memory-access power consumption is further reduced through the use of a small latch-based instruction and data caches at the first level of the hierarchy. Additional features that make this SoC a compact and self-contained system include on-chip ultra low power clock generation and analogue-to-digital conversion, as well as a set of peripherals, such as timers and serial interfaces able to work at the minimum voltage supply.
“This breakthrough technology can enable the development of an entirely new generation of microprocessors for wireless sensors and implantable medical devices, where minimized power consumption and long battery life are absolutely critical,” said Alessandro Cremonesi, Strategy and System Technology Group Vice President and Advanced System Technology General Manager, STMicroelectronics. "Our work with MIT aspires to play a key role in expanding the industry’s horizons in ultra-low-power technologies.”
"We are excited that our collaborative project with STMicroelectronics has resulted in an ultra-low-power microprocessor SoC. MIT researchers and STMicroelectronics engineers worked together to develop and implement a number of architectural and circuit technique to reduce power consumption. The energy-efficient processor will enable a number of exciting sensor network applications such as embedded bio-medical systems" said Prof. Anantha Chandrakasan, Department Head of EECS at MIT.

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