All the latest quantum computer articles

See the latest stories on quantum computing from eeNews Europe

Monday, December 18, 2017

Intel adds first high bandwidth memory to Stratix FPGA family

By Nick Flaherty

Intel has launched the industry’s first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2) that gives ten times the bandwidth of today's DDR memories. 

As a result the Stratix 10 MX FPGA is aimed at high-performance computing (HPC), data centres, network functions virtualization (NFV), and broadcast applications that require hardware accelerators to speed-up mass data movements and stream data pipeline frameworks.

HBM2 was accepted by JEDEC in January 2016 and supports two 128-bit channels per die for a total of 8 channels and a width of 1024 bits in total. It specifies up to eight dies per stack and doubles pin transfer rates up to 2GT/s. This provides 256 GB/s memory bandwidth per package from up to 8 GB per package. 

In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can compress and accelerate larger data movements compared with stand-alone FPGAs. With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache Kafka and Apache Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.

“To efficiently accelerate these workloads, memory bandwidth needs to keep pace with the explosion in data,” said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. “We designed the Intel Stratix 10 MX family to provide a new class of FPGA-based multi-function data accelerators for HPC and HPDA markets.”

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512Gbyte/s with the integrated HBM2. HBM2 vertically stacks DRAM layers using silicon via (TSV) technology that sit on a base layer that connects to the FPGA using high density micro bumps. This uses Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM to link the HBM2 die to the monolithic FPGA fabric, solving the memory bandwidth bottleneck in a power-efficient manner.

Intel is shipping several Intel Stratix 10 FPGA family variants, including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor). The Intel Stratix 10 FPGA family is built on Intel’s 14 nm FinFET manufacturing process and incorporates state-of-the-art packaging technology, including EMIB interconnect.

A third generation,  HBM3, has been specified but is not expected to come to market until 2020.

Related stories:

No comments: