Rambus is sampling the first functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype for the next-generation DDR5 memory technology.
This represents a key milestone for Rambus as the industry’s first silicon-proven memory buffer chip prototype capable of achieving the speeds required for the upcoming DDR5 standard.
“Data-intensive applications like Big Data analytics and machine learning will be key drivers for the adoption of DDR5, with enterprise close behind,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remain on the leading edge of industry standards.”
According to JEDEC, next-generation DDR5 memory will offer improved performance and power efficiency, providing double the bandwidth and density over DDR4. With that, server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance. This Server DIMM chip prototype uses the signal integrity and low-power, mixed-signal design expertise of Rambus to enable development of next-generation data centres.
The new features in DDR5 will target the specific problems being caused by the exponential growth in data generated by IoT, cloud services and real-time data analytics, and address the need to continuously process, move, and analyse that data faster. These enhancements are expected to include higher density, a new command structure and new power saving features. DDR5 will also likely introduce signal equalisation and error correction, and these will work their way down to industrial designs.
“Data-intensive applications like Big Data analytics and machine learning will be key drivers for the adoption of DDR5, with enterprise close behind,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remain on the leading edge of industry standards.”
According to JEDEC, next-generation DDR5 memory will offer improved performance and power efficiency, providing double the bandwidth and density over DDR4. With that, server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance. This Server DIMM chip prototype uses the signal integrity and low-power, mixed-signal design expertise of Rambus to enable development of next-generation data centres.
The new features in DDR5 will target the specific problems being caused by the exponential growth in data generated by IoT, cloud services and real-time data analytics, and address the need to continuously process, move, and analyse that data faster. These enhancements are expected to include higher density, a new command structure and new power saving features. DDR5 will also likely introduce signal equalisation and error correction, and these will work their way down to industrial designs.
The Rambus Memory and Interface Division looks at the power, performance, and capacity challenges of the communications and data centre computing markets with standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services.
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