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Thursday, September 07, 2017

Low voltage 64Mbit memory reduces power consumption in battery-powered devices

Microchip has launched a 64Mbit 1.8V Serial Quad I/O memory device that can reduce power consumption in battery powered devices. 

The SST26WF064C combines Dual Transfer Rate (DTR) with proprietary SuperFlash NOR Flash technology, targeting wireless and battery-powered applications. DTR gives the ability to output data on both edges of the clock which reduces overall data access time and power consumption. 

The SuperFlash technology also reduces power consumption by providing fast erase times. Typical chip-erase time for the SST26WF064C is between 35 and 50 milliseconds, compared to competitive Flash devices which take more than 30 seconds to erase. This also has high endurance cycling of up to 100,000 erase/write cycles and data retention of over 100 years.

The SST26WF064C also integrates a hardware-controlled reset functionality enabling a robust device reset. Most serial Flash devices in the market do not support hardware reset function due to pin-count limitations on the package. With this device, there is the option to reconfigure the HOLD# pin for this reset function.

Operating at frequencies reaching 104 MHz, the device enables minimum latency eXecute-In-Place (XIP) capability without the need for code shadowing on Static Random Access Memory (SRAM). 

It also uses a 4-bit multiplexed I/O serial interface to boost performance while maintaining the compact form factor of standard serial Flash devices. The SST26WF064C also supports full command-set compatibility with traditional Serial Peripheral Interface (SPI) protocol.

The memory is offered in a variety of package options including an 8-contact WDFN (6 mm x 5 mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC (7.50 mm) and 24-ball TBGA (8 mm x 6 mm).

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