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Monday, March 19, 2018

Xilinx looks to create new class of progammable device for AI

By Nick Flaherty

FPGA pioneer Xilinx is looking to create a new class of programmable device optimised for machine learning and artificial intelligence (AI) with dynamic reconfigurability.

The Adaptive Compute Acceleration Platform (ACAP) is a multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. An ACAP’s adaptability, which can be done dynamically during operation, delivers higher levels of performance and performance per-watt than CPUs or GPUs.

ACAP has been under development for four years at an accumulated R&D investment of over $1bn says Peng, with over 1,500 hardware and software engineers at Xilinx designing “ACAP and Everest.”  Software tools have been delivered to key customers. “Everest” will tape out in 2018 with customer shipments in 2019.
The devices are aimed at applications such as video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. 

The first ACAP product family, codenamed “Everest”, will be developed in TSMC 7nm process technology and will tape out later this year.

“This is a major technology disruption for the industry and our most significant engineering accomplishment since the invention of the FPGA,” says Victor Peng, president and CEO of Xilinx. “This revolutionary new architecture is part of a broader strategy that moves the company beyond FPGAs and supporting only hardware developers. The adoption of ACAP products in the data center, as well as in our broad markets, will accelerate the pervasive use of adaptive computing, making the intelligent, connected, and adaptable world a reality sooner.”

ACAP has – at its core – a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). 

It also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, high speed SerDes technology and RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant.

Software developers will be able to target ACAP based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.

“This is what the future of computing looks like,” says Patrick Moorhead, Founder, Moor Insights & Strategy. “We are talking about the ability to do genomic sequencing in a matter of a couple of minutes, versus a couple of days. We are talking about data centers being able to program their servers to change workloads depending upon compute demands, like video transcoding during the day and then image recognition at night. This is significant.”

Everest is expected to achieve 20x performance improvement on deep neural networks compared to today’s latest 16nm Virtex VU9P FPGA. Everest-based 5G remote radio heads will have 4x the bandwidth versus the latest 16nm-based radios (although much of that will come from the move to 7nm).

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