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Tuesday, April 20, 2010

Altera heads to 28nm for Stratix V FPGA Family

28Gbit/s transceivers focus on bandwidth
Altera has announced its next-generation 28-nm Stratix V FPGA family as the industry's highest bandwidth FPGA. The FPGAs will offer up to 1.6Tbit/s of serial switching capability for new technology designs next year, using a leading-edge 28-nm process to reduce the cost and power of high-bandwidth applications.
Manufactured on TSMC's 28-nm High-Performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18x18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps. The devices also incorporate the industry's highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty. The family includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:
  • Stratix V GT FPGA –  integrated 28Gbit/s transceivers targeting 100G systems and beyond.
  • Stratix V GX FPGA – supports a wide range of applications with 600Mbit/s to 12.5Gbit/s transceivers.
  • Stratix V GS FPGA – Optimized for high-performance digital signal processing (DSP) applications with 600Mbit/s to 12.5Gbit/s transceivers.
  • Stratix V E FPGA – Highest density FPGA for ASIC prototyping, emulation or high-performance computing applications.
"The innovations we made in our fifth-generation Stratix family dramatically improve the density and I/O performance of our high-end devices, further strengthening the FPGAs' competitive position versus ASICs and ASSPs," said Vince Hu, vice president of product and corporate marketing at Altera Corporation. "Altera remains committed to solving the challenge of increasing bandwidth while staying within designer's cost and power requirements. From the core to the I/O, we touched all aspects of Stratix V FPGAs to ensure they deliver the highest level of performance, density and integration."

Built for Bandwidth
Stratix V GX and Stratix V GS FPGAs feature up to 66 high-performance, low-power transceivers operating up to 12.5Gbit/s. Stratix V FPGAs support and meet compliance for a multitude of 3G, 6G and 10G protocols and electrical standards such as 10G/40G/100G, Interlaken and PCI Express (PCIe) Gen3, Gen2, Gen1. The devices also provide direct interoperability to 10G backplanes (10GBASE-KR) and optical modules. Stratix V GT FPGA's 28Gbit/s transceivers are designed to meet the CEI-28G specification. The 28-Gbps transceivers consume only 200 mW per channel, dramatically reducing a system's power-per-bandwidth profile.
In addition to transceiver bandwidth, Stratix V FPGAs include a 7 x 72-bit 1,600-Mbps DDR3 memory interface and LVDS channels capable of operating at 1.6 Gbps on ubiquitous I/Os.
Altera made several enhancements to the Stratix V FPGA's core architecture to increase area and logic efficiency and system performance, including:
  • New adaptive logic module (ALM) architecture – adds up to 800K additional registers in the largest device to maximize logic efficiency. The ALM architecture is ideal for heavily pipelined and register-rich designs.
  • Enhanced embedded memory structure featuring M20K blocks – offers improved area efficiency and higher performance.
  • Industry's first variable-precision DSP block – provides the highest efficiency and performance across multiple-precision DSP data paths.
  • User friendly partial reconfiguration – allows designers to reconfigure part of the FPGA while other sections remain running.
To view additional information regarding the Stratix V FPGA architecture, visit
Stratix V FPGAs include the highest level of hard IP integration on any FPGA, increasing the device's capabilities without incurring a power or cost penalty. Hardened functions in the device include PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO® (SRIO) 2.0 and 10 Gigabit Ethernet (GbE) 10GBASE-R. Memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+.
As announced earlier this year in Altera's innovations for 28-nm FPGAs announcement, Stratix V FPGAs feature the company's Embedded HardCopy Blocks. This gives Altera the ability to quickly change hardened functions within the FPGA, enabling the development of application-targeted device variants in three to six months. Embedded HardCopy Blocks provide customers the equivalent of 700K additional LEs with 65 percent lower power compared to a soft logic implementation.

Path to HardCopy V ASICs
Altera also provides Stratix V FPGA customers a low-risk, low-cost path to ASIC production with HardCopy V ASIC devices. Details regarding HardCopy V ASICs will be available at a later date.

Altera expects to begin shipping samples of Stratix V FPGAs in Q1 2011. Stratix V FPGAs will be supported with Quartus II software version 10.0 in Q2 2010.
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